TXT

JUDGE

By Elizabeth Wright,2014-10-25 05:33
11 views 0
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity judge is port(a,b:in std_logic_vector(6 downto 0); agree1,oppose1,abstain1,invalid1:out std_logic_vector(2 downto 0)); end judge; architecture one of judge is begin process(a,b) variable cnt1,cnt2,cnt3,cnt4:std_logic_vector(2 downto 0); begin cnt1:="0..

library ieee;

    use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity judge is

     port(a,b:in std_logic_vector(6 downto 0);

     agree1,oppose1,abstain1,invalid1:out std_logic_vector(2 downto 0));

    end judge;

    architecture one of judge is begin

    process(a,b)

    variable cnt1,cnt2,cnt3,cnt4:std_logic_vector(2 downto 0);

    begin

    cnt1:="000";

    cnt2:="000";

    cnt3:="000";

    cnt4:="000";

    for i in 0 to 6 loop

    if a(i)='0'and b(i)='1' then cnt1:=cnt1+1;

    elsif a(i)='1' and b(i)='0' then

    cnt2:=cnt2+1;

    elsif a(i)='0'and b(i)='0' then cnt3:=cnt3+1;

    elsif a(i)='1'and b(i)='1' then cnt4:=cnt4+1;

    end if;

    end loop;

    agree1<=cnt1;

    oppose1<=cnt2;

    abstain1<=cnt3;

    invalid1<=cnt4;

end process;

    end one;

Report this document

For any questions or suggestions please email
cust-service@docsford.com