FIB Specification - Picosecond Timing Project

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University of Chicago Argonne National Lab Picosecond Time-of-Flight System Clock Distribution Subsystem

University of Chicago Argonne National Lab

    Picosecond Time-of-Flight System

    Clock Distribution Subsystem

    -- --

    thAugust 15, 2007

    Version 0.3

     11 1John T. Anderson, Karen Byrum, Gary Drake,2223Henry J. Frisch, Jean-Francois Genat, Harold Sanders, Fukun Tang

1 High Energy Physics Division, Argonne National Laboratory, 9700 S. Cass Ave, Lemont, IL 2 Enrico Fermi Institute, University of Chicago, 5640 S. Ellis Ave, Chicago, IL



1) Version 0.1, initial draft of document, 5 August 2007.

    2) Version 0.2, issued 9 august 2007.

    a) Replaced Figure 3 sketch with better, to-scale version showing both DAQ and Analog


    b) Modified clock chip discussion to include new information provided by Jean-Francois. c) Added new clock chip information about TI CDCE62005.

    3) Version 1.0, issued 16 August, 2007.

    a) First “real” version after review and input from rest of group.

    b) Fixed title page to correctly show all authors and institutions involved in this effort. c) Revised System Introduction paragraphs per notes from H. Frisch.

    d) Updated Figure 1 to clarify and add missing high voltage lines.

    e) Corrected “link” terminology, explicitly defined each link in system diagram.

    f) Added short textual description of each link, named each link.

    g) Added requested table defining each signal in each link, including estimated connector


    h) Stripped out technical details with formal language from section 2. Created new section 4

    to hold technical detail information until such data is moved from this document into

    separate engineering documents specific to each link or module.

    i) Added LVDS implementation picture to complement those of LVPECL and CML already

    in document.

    j) Added additional introductory information describing the overall functions of the Modules,

    including information about the Time Stretcher chip, in addition to that of the Links.


    This document describes the Clock Distribution sub-system of the Picosecond Time-of-Flight system. The Clock Distribution sub-system encompasses the receipt of the system clock from a source external to Time-of-Flight system, through the generation of the Acquire Clock that is provided to the Time Stretcher chips.

    1.1 System Introduction

    The Picosecond Time-of-Flight electronics system consists of a custom ASIC and several commercial chips integrated with a micro-channel plate (MCP) photo-detector that is designed to measure the arrival time of charged particles with a design goal of one picosecond resolution. Effectively, the system acts as a "digital phototube"; all analog signal processing is performed directly by the circuits mounted on the MCP such that the only interfaces that connect to external data collection systems are digital control, digital data output and power supplies. The Picosecond Time-of-Flight system consists of a series of Modules which are connected by Links, where by the term Link we mean all of the interconnecting signals between two Modules. Figure 1 gives the overall system picture.





    Figure 1 - Overall System Picture

    1.1.1 Description of Modules in the System

    The DAQ board holds interface chips, power supply regulators and an FPGA. Its purpose is to provide interface to the rest of the data acquisition system and provide infrastructure support to the Analog board. The Analog board connects directly to the MCP phototube. The Analog Board takes the Master Clock and uses a commercial clock distribution chip to create a 1GHz Acquire Clock. It contains a set of “Time Stretcher” chips that receive the fast signals from the anodes of the MCP tube. The Time Stretcher chips create Time Data pulses whose width is proportionate (200:1) to the delay between the arrival of the signal from the MCP and the next nd(or 2 next) edge of the Acquire Clock by means of an internal PLL and counter running at 5GHz. This is the “common stop” mode of time digitization. The FPGA on the DAQ board measures the

    width of these pulses and provides digital data readout of the pulse width upon demand. 1.1.2 Description of Communications Links in the System

    The CTL/PWR Link is the interface between the DAQ board and the rest of the experiment electronics. Bulk DC power is input to the DAQ board, where it is regulated for local

    use and re-distributed to the Analog Board. High voltage bias for the MCP is provided external to the DAQ board and is routed through the two boards to the MCP without being used on either board. The System Clock is the main clock that is distributed to all picosecond time-of-flight systems, and is the source of all other clocks within this system. The Ctrl/Data signal(s) provide the method by which the experiment controls the Time-of-Flight system and obtains the data transmitted by the DAQ board.

    The Interboard Link is a set of mated connectors between the DAQ board and the Analog board. The DAQ board generates the Master Clock from the System Clock, passes regulated DC and high voltage power to the Analog board, and generates any control signals needed by chips on the Analog board. In return, the Analog board generates an FPGA reference clock from the Master Clock and sends varying-width Time Data pulses to the FPGA on the DAQ board.

    The Analog board mounts directly upon the MCP tube. The anodes of the tube provide analog signal input to the Analog board, and the tube‟s high voltage bias is provided by contacts

    of the Analog board.

    1.1.3 Tabular Description of all signals in each Link

    The following tables enumerate the conductor counts and signal levels for all the defined signals in each Link. Specific description of the implementation of each Link (e.g. part numbers, connector types, wire gauges, shielding, etc.) are not listed here but are found in separate documentation specific to each Link.

Signal Name Number of Signal Levels Notes, Special Considerations

    Conductors and/or Protocols

    System Clock 2 LVDS Frequency must be integer divisor of

    1GHz; 62.5MHz assumed for tests.

    CTRL/DATA 6 LVDS Pair 1: control data into FPGA

    Pair 2: readout enable in

    Pair 3: readout data

    Control & data are serial.

    Bulk DC Power 4 +3.3V and GND All other voltages in the system are

    regulated from the bulk +3.3V


    HV Bias Power 2 3kV and GND Subminiature connector type may be

    required due to board size. HV

    GND is routed separately from

    return planes of DAQ and Analog

    boards, but is tied to LV GND at

    MCP tube.

    Table 1 - Enumeration of signals within the CTL/PWR Link

Signal Name Number of Signal Levels Notes, Special Considerations

    Conductors and/or Protocols

    The total number of conductors in the Interboard Link is determined by the

    number of pins in the connectors between boards. The counts below are

    based upon the use of four connectors of 16 pins (total = 64 conducto