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    CAPSL

    Computer Architecture and Parallel Systems Laboratory Department of Electrical and Computer Engineering

    GUANG R. GAO

    University of Delaware

    Department of Electrical and Computer Engineering

    140 Evans Hall

    Newark, DE 19716

    Tel: (302)831-8218

    Fax: (302)831-4316

    ggao@capsl.udel.edu

    http://www.capsl.udel.edu

    EDUCATION

    PhD Degree in Electrical Engineering and Computer Science

    Massachusetts Institutes of Technology, August 1986.

    Member of Computational Structures Group at Laboratory of Computer Science, MIT,

    June 1982 to August 1986.

MS Degree in Electrical Engineering and Computer Science

    Massachusetts Institutes of Technology, June 1982.

BS Degree in Electrical Engineering

    Tsinghua University, Beijing.

    PROFESSIONAL EXPERIENCE

    University of Delaware

    Newark, DE, USA.

    Endowed Distinguished Professor, Department of Electrical and Computer Engineering, steffective from Sept. 1, 2005.

University of Delaware

    Newark, DE, USA.

    Professor, Department of Electrical and Computer Engineering, Sept. 1996 Present.

    Founder and leader of the Computer Architectures and Parallel Systems Laboratory

    (CAPSL).

McGill University

    Montreal, Canada

    Associate Professor, School of Computer Science, Jun. 1992 - Aug. 1996.

    Assistant Professor, School of Computer Science, Aug. 1987 - Jun. 1992.

    Founder and leader of the Advanced Compilers, Architectures and Parallel Systems Group

    (ACAPS) at McGill since 1988.

Center of Advanced Studies, IBM Toronto Lab

    Aug. 1993 - Jun. 1994.

    Visiting scientist with a NSERC Senior Industrial Fellowship.

    CAPSL

    Computer Architecture and Parallel Systems Laboratory Department of Electrical and Computer Engineering

    Philips Research Laboratories

    Sept. 1986 - Jun. 1987.

    Briarcliff Manor, NY, US.

    Senior member of research staff of the Computer Architecture and Programming Systems

    Group. Played a major role in founding a multiprocessor system project, and research

    in parallelizing compilers.

Massachusetts Institutes of Technology

    Jun. 1994 - Aug. 1994

    Visiting Professor (Sabbatical)

    Jun. 1980 - Aug. 1986

    Member of the Computational Structures Group at the Laboratory of Computer Science,

    MIT.

    Participated in the MIT Static Dataflow Architecture Project and other projects. Proposed

    a novel methodology of organizing array operations to exploit the fine-grain parallelism

    of dataflow computation models. Developed a unique pipelined code mapping scheme

    for dataflow machines (later known as dataflow software pipelining).

    CURRENT RESEARCH AREAS

    ; Computer Architecture and Parallel Systems.

    ; Optimizing and Parallelizing Compilers.

    ; Runtime systems.

    ; Applications: Bio-Informatics and High Performance Computing.

    PROFESSIONAL MEMBERSHIP

    Senior Member of IEEE, Member of ACM, ACM-SIGARCH, ACM-SIGPLAN.

    NATIONAL AND INTERNATIONAL RECOGNITION

    ; ACM Fellow.

    ; IEEE Fellow.

    ; IEEE Computer Society Distinguished Visitor, 1998-2001.

    ; Elected as a chairman of a collection of well recognized international conferences in

    computer/information sciences and engineering (see list).

    ; Invited as a Keynotes Speaker of a number of recognized international conferences (e.g. IPDPS

    2005, HiPC2005, IWOMP2006, NPC2007, GCC2009).

    ; Elected as a Distinguished Professor of Electrical and Computer Engineering with a Named

    Professorship at University of Delaware.

    CITATIONS AND SPECIAL APPOINTMENTS

    ; Citation from IEEE Fellowship: For contributions to multiprocessor computers and compiler

    optimization techniques.

    ; Citations from ACM Fellowship: For contributions to architecture and compiler technology of

    parallel computers.

    CAPSL

    Computer Architecture and Parallel Systems Laboratory Department of Electrical and Computer Engineering

    ; Gao’s publications have been cited widely in his field. For example, there are well over 500

    citations for his top 5 most cited papers. Gao’s work has attracted the attention of many

    researchers in diverse application areas. The impact of his work is apparent through the impact

    of his work in his areas and several modifications and extensions from of the approaches and

    algorithms pioneered by his work.

    He has many special appointments most are evident on the list of recognized international

    conferences where he has been appointed as chairman or technical program committee

    members, or editorships on prestigious journal as listed below.

    He also has received honorable appointments. For example, he has served as a panelist of many

    international conference panels and National Science Foundation grant review panels,

    external Ph.D thesis examiners both within US and internationally (detailed list can be

    submitted on request). He also held honorable special visiting professorships in several

    universities in China especially the prestigious Tsinghua University (since 2007).

    Most recently, he has been invited to server in an international review panel in Computer

    Science field of Tsinghua University (together with 4 other internationally well recognized

    computer scientists holding prestigious titles such National Academy of Enginnering (NAE)

    member, AAAS Fellow, Royal Academy of Engineering Fellow, Founder member of the Scientific

    Council of the European Research Council)

    CONFERENCE COMMITTEE CHAIRMANSHIP

    ; Advisor Board, International Conference on Parallel Processing (Europar’12)

    ; Program Chairman of the 40th International Conference on Parallel Processing (ICPP’11),

    Taipei, Taiwan.

    ; Panel Coordinator, International Conference on Parallel Architectures and Compiler Technology

    (PACT 2011); Data-Flow Execution Models for Extreme Scale Computing (DFM 2011). ; Advisor Board, International Conference on Parallel Processing (Europar’11)

    ; Program Co-Chair of the 22nd Workshop on Language and Compilers for Parallel Computing

    (LCPC’10), Oct 2009 in Newark, DE,USA,

    ; Program Co-Chair of IFIP International Conference on Network and Parallel Computing

    (NPC’09), October 19 to 21, 2009 in Gold Coast, Australia

    ; Vice Program Chairman of the 36th International Conference on Parallel Processing (ICPP’07),

    September 10-14, 2007 in XiAn China

    ; Program Chairman of International Workshop on OpenMP (IWOMP'2007), June 3rd - June 7th,

    2007 in Beijing, China

    ; General Chair of International Conference on Embedded and Ubiquitous Computing (EUC’04),

    August 26-28, 2004 in Aizu, Japan

    ; Program Co-Chair of IFIP International Conference on Network and Parallel Computing

    (NPC’04), Oct 18 - 20, 2004 in Wuhan, China

    ; Program Vice-Chair of International Parallel & Distributed Processing Symposium

    (IPDPS’04), April 30, 2004 in Santa Fe, New Mexico

    ; Program Vice-Chair of International Conference on High Performance Computing (HiPC’01),

    Dec 17 20, 2001 in The Taj Krishna in Hyderabad, India

    ; Program Co-Chair of the Compilers, Architectures and Synthesis for Embedded Systems

    (CASES’01), November 16 - 17, 2001 in Atlanta, Georgia, USA

    ; Chair of the Third Workshop on Petaflop Computing, Feb. 1999 in Annapolis, MD. ; Co-Chair of the Multithreaded Architecture Workshop, in Conjunction to HPCA’99, Jan. 1999 in

    Orlando, Florida

    CAPSL

    Computer Architecture and Parallel Systems Laboratory Department of Electrical and Computer Engineering

    ; General Co-Chair of the 1998 International Conference on Parallel Architectures and

    Compilation Techniques (PACT’98), Oct. 1998 in Paris, France., co-sponsored by IFIP and IEEE

    Computer Society

    ; Co-Chair of the Compiler and Architecture Support for Embedded Systems (CASES’98, 99), in

    Washington D.C.

    ; Program Chairman of the 1994 International Conference on parallel Architectures and

    Compilation Techniques (PACT’94), Aug. 1994 in Montreal, Canada.

    JOURNAL EDITORSHIP

    ; Editorial Board of Journal of Chinese Computer Research and Development (2005 - ). ; Editorial Board of the Journal of Embedded Computing (2004 - ).

    ; Editorial Board of the International Journal of High Performance Computing and Networking

    (2003 - ).

    ; Parallel Processing Letters (2001 - ).

    ; Editorial Board of IEEE Transactions on Computers (1998 - 2001).

    ; Editorial Board of IEEE Concurrency Journal (1997 - 2000).

    ; Editorial Board of the Journal on Programming Languages in Jan. 1996, and subsequently

    became one of the two Co-Editors of the journal (1997-1998).

    ; Guest Editor for the Special Issue on IEEE Transaction on Computers, Journal of Parallel and

    Distributed Computing, etc.

    PROGRAM COMMITTEE MEMBERS OF RECOGNIZED INTERNATIONAL

    CONFERENCES

    ; International Conference of Parallel Processing ( ICPP’12).

    ; International Conference on Parallel Architectures and Compiler Technology (PACT 2012);

    Data-Flow Execution Models for Extreme Scale Computing (DFM 2011, 2012). ; IFIP International Conference on Network and Parallel Computing (NPC’04, 05, 06, 09, 10, 11,

    12)

    ; International Workshop on Languages and Compilers for Parallel Computing (LCPC 2010, 2011,

    2012).

    ; International Symposium on Code Generation and Optimization (CGO’11, CGO’12).

    ; International Workshop on OpenMP (IWOMP'06, 07, 08, 09, 10, 11, 12).

    ; Programming Language Design and Implementation (PLDI); Open64 Workshop’12.

    ; Programming Language Design and Implementation (PLDI); Multicore and GPU Programming

    Models, Languages and Compilers Workshop (PLC’12).

    ; ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming (PPoPP

    2010).

    ; Workshop on Multithreaded Architectures and Applications (MTAAP 07, 08, 09, 10, 11, 12). ; IFIP and ACM SIGARCH International Conference on Parallel Architectures and Compilation

    Techniques (PACT’94, 95, 96, 97, 98, 99, 00, 01, 07, 10, 11, 12).

    ; IFIP Working Conference on Distributed and Parallel Embedded Systems (DIPES’06, 07, 08, 09,

    10, 11).

    ; Workshop on Programmability Issues for Multi-Core Computers (MULTIPROG’08, 09, 10, 11, 12)

    ; International Conference on High-Performance Embedded Architecture and Compilation

    (HiPEAC 2009).

    ; ACM Computing Frontiers (CF 2008).

    ; Asia-Pacific Computer Systems Architecture Conference (ACSAC’06, 07, 08).

    CAPSL

    Computer Architecture and Parallel Systems Laboratory Department of Electrical and Computer Engineering

    ; International Conference on Parallel Processing (ICPP’07).

    ; ACM/IEEE International Conference for High Performance Computing and Communications

    (SC07, 08, 09, 10, 11).

    ; ACM/IEEE International Workshop on High-Level Parallel Programming Models and Supportive

    Environments (HIPS 2007).

    ; ACM International Conference on Supercomputing (ICS’95, 02, 03, 04, 06, 07, 08).

    ; IEEE International Parallel and Distributed Processing Symposium (IPDPS’01, 02, 03, 06, 10).

    ; Fifth IEEE International Workshop on High Performance Computational Biology (HiCOMB’06).

    ; ACM International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN

    2005).

    ; ACM/IEEE International Symposium on Micro architectures (MICRO’95, 96, 97, 02).

    ; High Performance Computing Symposium (HPCS’95, 96, 98, 99, 01, 02).

    ; International Conference on Parallel Processing (EURO-PAR’95, 96, 01).

    ; Compilers, Architectures and Synthesis for Embedded Systems (CASES’00, 01).

    ; IEEE International Symposium on High Performance Computer (HPCA’97, 99, 00).

    ; International Conference on Compiler Construction (CC’98, 99, 00), Europe.

    ; Working Conference on Massively Parallel Programming Models (MPPM’93, 95, 97, 99).

    ; International Symposium on High Performance Computing (ISHPC’99), Japan.

    ; ACM Symposium on Programming Language Design and Implementation (PLDI’98).

    ; International Parallel Processing Symposium (IPPS’95).

    ; IEEE International Conference on Algorithms and Architectures for Parallel Processing

    (ICAPP’95).

    ; Parallel Architecture and Language Europe (PARLE’91, 92, 93, 94, 95).

    PANEL OF INTERNATIONAL CONFERENCES AND MEETINGS

    Invited as a panel chair or a panelist in panels of many international conferences and meetings.

    INVITED SEMINARS AND DISTINGUISHED SEMINARS (Partial)

    Given seminars in many industrial and academic organizations: ; IBMT.J. Watson Research Center

    ; IBM Toronto Lab,

    ; AT&T Bell Laboratories

    ; BNR

    ; HP Labs

    ; Intel

    ; SGI

    ; DEC

    ; QualComm

    ; NRL (Navy Research Lab.)

    ; JPL (Jet Propulsion Laboratory)

    ; Sandia National Laboratory

    ; Oak Ridge National Laboratory

    ; NASA Ames Research Center

    ; PNNL (Pacific Northwest National Laboratory) ; MIT

    CAPSL

    Computer Architecture and Parallel Systems Laboratory Department of Electrical and Computer Engineering

    ; Stanford University

    ; UC Berkeley

    ; NYU

    ; Cornell University

    ; University of Maryland

    ; University of Alberta

    ; University of Colorado

    ; University of Southern California

    ; University of Toronto

    ; University of Victoria

    ; University of Michigan

    GRANTS AND OTHER REVIEW FUNCTIONS

    ; Invited as National Science Foundation (NSF) grant review panels (many times) ; Invited as an external reviewer of a grant reviewer to NSF-equivalent organizations in other

    countries (Canada, England, Holland, France, etc.)

    ; Invited as a reviewer for tenure and other promotion reviewers for professors/scientists both

    in US and beyond.

    ; Invited as external Ph.D thesis examiners both within US and internationally (e.g. INRIA

    (France), Chamers University (Sweden), Tsinghua University (China), Chinese University of

    Science and Technology (China), Huazhong University of Science and Technology (China), etc.).

    Section A: Teaching and Research Supervision

    A.1: TEACHING

    A series of new courses have been introduced and taught over years. The topics include: 1. Computer Architectures

    2. Parallel Computing

    3. Parallel and Functional Programming

    4. Optimizing and Parallelizing Compilers

    5. Discovery Informatics and High-Performance Computing

    For a detailed course listing, please see http://www.capsl.udel.edu/

    A.2: RESEARCH SUPERVISION

    Current, graduate students under my supervision include:

1. Mark Pellegrini (Performance Analysis).

    2. Andrew Russo (TBD).

    3. John Tully (TBD).

    4. Wesley Toland (TBD).

    5. Juergen Ributzka (Compilers) (2009 2013 Expected).

    6. Brian Lucas (High Performance IO) (2007 2012 Master Expected).

    7. Thomas St. John (Parallel Graph Algorithms) (2007 2012 Master Expected).

    CAPSL

    Computer Architecture and Parallel Systems Laboratory Department of Electrical and Computer Engineering 8. Chris Adamopoulos (Compilers) (2007 Master Expected). 9. Kelly Livingston (Computer Architecture and Parallel Application) (2007 2013 Expected) 10. Sunil Shrestha (Compilers) (2007 2013 Expected). 11. Elkin Garcia (Parallel Applications) (2008 2013 Expected). 12. Joshua Suetterlein (TBD) (2010 2015 Expected).

    13. Aaron M. Landwehr (TBD) (2010 2015 Expected). 14. Robert Pavel (Parallel Simulation) (2010 2015 Expected). 15. Joshua B. Landwehr (TBD) (2010 2013 Expected). 16. Yao Wu (Big Data) (2011 2015 Expected).

    17. Jaime Arteaga (TBD) (2013-2017 Expected). 18. Sergio Pino (TBD) (2013-2017 Expected).

    Current Postdoc fellows under my supervision include:

1. Stéphane Zuckerman (2010 present).

    2. Chen Chen (2011 present).

    3. Souad Koliai (2012 present).

    4. Long Zhen (2012 present).

    5. Haitao Wei (2012 present).

    Already Completed:

    The following Graduate students and Post-Docs have already completed their proposed research under

    my supervision:

    PhD Level:

    1. Daniel Orozco

    TIDeFlow: A Dataflow-inspired execution model for high performance computing programs

    University of Delaware (USA), 2007 2012.

2. Joseph B. Manzano

    A comparison between virtual code management techniques

    University of Delaware (USA), 2003 2011.

    3. Ge Gan

    Programming model and execution model for OpenMP on the Cyclops-64 manycore processor

    University of Delaware (USA), 2004 2010.

4. Long Chen

    Exploring novel many-core architectures for scientific computing

    University of Delaware (USA), 2005 2010.

5. Fei Chen

    Enabling system validation for the many-core supercomputer

    University of Delaware (USA), 2001 2009.

6. Juan del Cuvillo

    Breaking away from the OS shadow: A program execution model aware thread virtual machine for

    multicore architectures

    University of Delaware (USA), 2001 2008.

7. Yuan Zhang

    Static analyses and optimizations for parallel programs with synchronization

    CAPSL

    Computer Architecture and Parallel Systems Laboratory Department of Electrical and Computer Engineering

    University of Delaware (USA), 2002 2008.

8. Mihailo Kaplarevic

    Environmental genome informational utility system (EnGENIUS)

    University of Delaware (USA), 2001 2007.

9. Weirong Zhu

    Efficient synchronization for a large-scale multi-core chip architecture

    University of Delaware (USA), 2002 2007.

10. Rishi Lee Khan

    Engineering systems neuroscience: Modeling of a key adaptive brain control system involved in

    hypertension

    University of Delaware (USA), 2000 2007.

11. Alban Douillet

    A compiler framework for loop nest software-pipelining

    University of Delaware (USA), 2001 2006.

12. Yanwei Niu

    Parallelization and performance optimization of bioinformatics and biomedical applications

    targeted to advanced computer architectures

    University of Delaware (USA), 2001 2005.

13. Robel Y. Kahsay

    Advanced protein sequence analysis methods for structure and function prediction

    University of Delaware (USA), 2001 2005.

14. Andres Marquez

    The CARE architecture

    University of Delaware (USA), 1995 2004.

15. Hongbo Yang

    Power-aware compilation techniques for high performance processors

    University of Delaware (USA), 1999 2003.

16. Parimala Thulasiraman

    Irregular computations on fine-grain multithreaded architecture

    University of Delaware (USA), 1995-2000.

17. Xinan Tang

    Compiling for multithreaded architectures

    University of Delaware (USA), 1995 1999.

18. Kevin Bryan Theobald

    EARTH: An Efficient Architecture for Running Threads

    McGill University (Canada), 1990 1999.

19. Erik Richter Altman

    Optimal software pipelining with function unit and register constraints

    McGill University (Canada), 1991 1996.

20. Shashank Nemawarkar

    Performance modeling and analysis of multithreaded architectures

    McGill University (Canada), 1989 1996.

    CAPSL

    Computer Architecture and Parallel Systems Laboratory Department of Electrical and Computer Engineering

21. Vugranam C. Sreedhar

    Efficient program analysis using DJ graphs

    McGill University (Canada), 1990 1995.

22. Guy Tremblay

    Parallel implementation of lazy functional languages using abstract demand propagation

    McGill University (Canada), 1988 1994.

23. Qi Ning

    Register allocation for optimal loop scheduling

    McGill University (Canada), 1990 1993.

24. Herbert H. J. Hum

    The Super-Actor Machine: A hybrid dataflow/von Neumann architecture

    McGill University (Canada), 1990 1992.

25. Robert Kim Yates

    Semantics of timed dataflow networks

    McGill University (Canada), 1988 1992.

    MS Level:

1. Thomas St. John

    Massively Parallel Breadth First Search Using a Tree-Structured Memory Model

    University of Delaware (USA), 2007 2013.

2. Joshua Landwehr

    Tapestry: Weaving Execution and Synchronization Models

    University of Delaware (USA), 2009 2013.

3. Sunil Shrestha

    Parallel Low-Overhead Data Collection Framework for a Resource Centric Performance Analysis

    Tool

    University of Delaware (USA), 2007 2012.

4. Xiaomi An

    Memory State Flow Analysis and Its Application

    University of Delaware (USA), 2009 2011.

5. Juergen Ributzka

    Toward a software pipelining framework for many-core chips

    University of Delaware (USA), 2005 2009.

6. Jonathan L. Barton

    Hardware implementation of a synchronization state buffer in VHDL

    University of Delaware (USA), 2005 2008.

7. Mark Pellegrini

    A case study of the Mstack cross-platform benchmark on the Cray MTA-2

    University of Delaware (USA), 2004 2008.

8. Matthew Wells

    University of Delaware (USA), 2006 - 2008.

    CAPSL

    Computer Architecture and Parallel Systems Laboratory Department of Electrical and Computer Engineering

9. Yi Jiang

    Design and implementation of tool-chain framework to support OpenMP single source compilation

    on cell platform

    University of Delaware (USA), 2006 2008.

10. Long Chen

    Optimizing the Fast Fourier Transform on a many-core architecture

    University of Delaware (USA), 2005 2008.

11. Liping Xue

    Efficient mapping of fast Fourier transform on the Cyclops-64 multithreaded architecture

    University of Delaware (USA), 2005 2007.

12. Ge Gan

    CDP: A multithreaded implementation of a network communication protocol on the Cyclops-64

    multithreaded architecture

    University of Delaware (USA), 2004 2007.

13. Eun Jung Park

    Methodology of dynamic compiler option selection based on static program analysis:

    Implementation and evaluation

    University of Delaware (USA), 2004 2007.

14. Dimitrij Krepis

    A study of simulation and verification of a many-core architecture on two modern reconfigurable

    platforms

    University of Delaware (USA), 2004 2007.

15. Divya Parthasarathi

    Tower methodology for verification of multi-core architecture: A case study

    University of Delaware (USA), 2003 2005.

16. Ying Ping Zhang

    A study of architecture and performance of IBM Cyclops64 interconnection network

    University of Delaware (USA), 2003 2005.

17. Vishal Karna

    Multiprocessor SOC Verification

    University of Delaware (USA), 2002 2005.

18. Robert Klosiewics

    A Parallel Debugger for the Cyclops Architecture

    University of Delaware (USA), 2002 2004.

19. Inanc Dogru

    An integer linear programming approach to reduce register spills on itanium processors

    University of Delaware (USA), 2002 2004.

20. Xing Wang

    Quantitive Study of Human-Computer interaction in adaptive search on Mobile Handsets and its

    Localization for Mandarin Chinesse

    University of Delaware (USA), 2001 2004.

21. Weirong Zhu

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