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Preparation and characterization (Pb,Sr)TiO3 thin for ULSI DRAM ...

By Gordon Mills,2014-07-09 19:11
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Preparation and characterization (Pb,Sr)TiO3 thin for ULSI DRAM ...

    액적화학증착법을 이용하여 제조한 (Pb,Sr)TiO 박막의 특성분석 3

    정현진, 우성일

    한국과학기술원 화학공학과

    Characterization of (Pb,Sr)TiO thin films prepared by liquid source 3

     misted chemical deposition

    Hyun Jin Chung, Seong Ihl Woo

    Department of Chemical Engineering, KAIST

Introduction

     In order to overcome the limitation of conventional capacitor structure, ferroelectric thin films, for example Pb(Zr,Ti)O[1], SrBiTaO[2] and (Ba,Sr)TiO(BST)[3] have been 32293

    intensively studied for a number of integrated devices such as dynamic random access memories(DRAM) and non-volatile random access memories(NVRAM) because of high dielectric constant, large spontaneous polarization and low leakage current. Among the various ferroelectric films, BST thin film was noticed as the most promising material for the capacitor of ULSI DRAM cell due to its high dielectric constant and paraelectricity at normal operating temperature. Although BST possesses a satisfactorily high dielectric constant, BST capacitors have a rather low onset field for high current emission, i.e., only a 300-500kV/cm, which will limit its minimum thickness which can be applied. Also, it was known that a post-oheat-treatment at high temperature, 750C, was essential to obtain a good electrical property.

    The heat treatment at high temperature can make a deleterious effect on electrode, barrier metal and contact plug. Strontium titanate (SrTiO) is one of the few titanates which is cubic 3

    at room temperature. But, the dielectric constant is lower than BST. The addition of lead into strontium titanate makes its dielectric constant higher and the temperature of crystallization lower. Also, the curie point is retained to somewhere around or below room temperature, making (Pb,Sr)TiO (PST) a paraelectric material with a high dielectric constant. So, PST 3

    thin film can be a promising material for the capacitor of ULSI DRAM cell due to its high dielectric constant and paraelectricity at normal operating temperature.

    Experiment

     In this study, PST thin films were prepared by LSMCD method using Pb acetate i[Pb(OOCCH)], Sr acetate [Sr(OOCCH)], and Ti isoproxide [Ti(OCH)] as metallic 3232374

    precursors. These were dissolved in 1-butanol and 2-methoxyethnol. A ultrasonic nebulizer was used to make the mists of precursor solution. The mist was transported to a deposition chamber by carrier gas (Ar). The Si(100) and Pt coated Si(100), Si(100)/SiO(500nm)/ 2

    Pt(100nm), were used as a wafer.

    Result and discussion o As-deposited PST films (150nm thick) was baked at 400C and annealed in air at

    various temperatures for 5min by RTA. Their crystal structures were examined by XRD with

    oCu K; radiation as shown in Fig. 1. The crystallization was occurred at 500C. The

    polycrystalline phase such as (100), (110), (111) and (211) was formed. Also, PST film shows a preferred (110) orientation. The surface morphologies of PST thin films were orecorded by SEM in Fig. 2. The grains were formed above 500C. This result is consistent

    with that of XRD. It can be seen that the surface of PST film is very smooth, dense and ouniform without cracking and void. The mean grain size of the film annealed at 650C was

    about 23nm by Scherrers formula[4].

     The elemental component distribution of PST thin film and the contaminants on surface of PST thin film were obtained by using auger electron spectroscopy (AES) as shown in Fig. o3. Fig. 3(a) is the AES depth profile of PST thin film (100nm thick) annealed at 550C for

    5min. The component concentration is nearly uniform through the whole bulk of PST film. Also the high intensity of carbon was observed at the surface of PST thin film. Fig. 3(b) is othe AES depth profile of PST thin film (130nm thick) annealed at 650C for 5min. The

    intensity of carbon was smaller than that of (a) at the surface of PST thin film. However, the components of Pb and O were abnormal at the surface of PST thin film. It might be resulted ofrom the high mobility and high evaporation of Pb above 640C. However, the component

    concentration is nearly uniform through the whole bulk of PST film. The elemental composition of the deposited film at the various annealing temperatures was obtained by using WDS. The results revealed that the elemental composition of PST thin film is not much different with that precursor solution. The change in the composition was not occurred at the olower annealing temperature of below 640C. o The capacitance-voltage curves (at 100kHz) of the PST thin films annealed at 550C for

    5min in RTA are shown in Fig. 4, where the data were taken using a HP4192A impedance analyzer. The atomic ratios of Pb/(Pb+Sr) and Ti/(Pb+Sr) are 0.36 and 1.06, respectively. It shows a slightly ferroelectric property indicated by butterfly-type capacitance-voltage curve. The voltage of the highest capacitance is smaller than that of typical ferroelectric thin film such as PZT. The complete paraelectricity of PST thin film might be obtained by decrease of Pb content. The dielectric constant and dielectric loss obtained here are almost the same at 330 and 0.04 from 130 to 90nm at 0V, respectively. The dielectric constant decreased below 60nm thick. Its equivalent oxide thickness was similar about 0.9nm. The current-voltage ocharacteristics of the PST thin films annealed at 550C for 5min in RTA are shown in Fig. 5.

    The current-voltage curve on PST thin film was measured by using HP4145B picoampere current meter. The atomic ratios of Pb/(Pb+Sr) and Ti/(Pb+Sr) are 0.36 and 1.06, respectively. -62The leakage current density of PST thin film (90nm thick) is less than 5.5x10(A/cm) at a

    applied voltage of 1V. The lower leakage current density was obtained by using post-annealing under O. 2

Reference

    1. P. K. Larsen, G. J. M. Dormans, D. J. Taylor and P. J. van Veldhoven, J. Appl. Phys. 76,

2405 (1994).

    2. O. Auciello, A. R. Krauss, J. Im, D. M. Gruen, E. A. Irene, R. P. H. Chang and G. E.

    McGuire, Appl. Phys. Lett. 69, 2671 (1996).

    3. T. Kawahara, M. Yamamuka, A. Yuuki and K. Ono, Jpn. J. Appl. Phys. 35, 4880 (1996).

    4. H. Kawano, K. Morri and Y. Nakayama, J. Appl. Phys. 73, 5141 (1993).

    Fig. 1. XRD patterns of PST thin films on Si(100) wafer annealed at various temperatures.

Fig. 2. SEM photographs of PST thin films on Pt-coated Si(100) wafer annealed at

     various temperatures.

    6000

    40(fF/m5000

    130nm, 334

    0.4V-0.4V

    90nm, 337

    4000

    60nm, 270

    3000

    PtPt(a) (b) SiO(Pb,Sr)TiO23SiO(Pb,Sr)TiO23

    OOSrSrPbPbLower oxygen Ti2000at surfaceTiPtPtSiSi

    Atomic concentration (a.u.)Atomic concentration (a.u.)

    Pb surfacediffusion01234567890123456789

    Sputtering time (min)Sputtering time (min)carbon impurity rangecarbon impurity range

    ooFig. 3. AES depth profiles of PST thin films annealed at (a) 550C and (b) 650C for 5min

     in RTA.

     1000 2)

    2)

    Capacitance (pF)

    0-5-4-3-2-1012345

    Applied Voltage (V)

    Fig. 4. The capacitance-voltage curves (at 100kHz) of the PST thin films annealed at o 550C for 5min in RTA.

     -210

    )2-310

    -410Fig. 5. The current-voltage characteristics -510 of the PST thin film annealed at o 550C for 5min in RTA. -610130nm

    -710

    -81090nmLeakage current density (A/cm

    -910012345

    Applied voltage (V)20(fF/m60nm

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