Performance Analysis of a 60 GHz Near Gigabit
System for WPAN Applications
L. Rakotondrainibe, Y. Kokar, G. Zaharia, G. Grunfelder, G. El Zein
European University of Brittany (UEB), INSA, IETR - UMR CNRS 6164 INSA, 20 Avenue des buttes de Coesmes, CS 70839 -35708, Rennes cedex, France firstname.lastname@example.org
Abstract—A 60 GHz wireless Gigabit Ethernet (G.E.) gain antennas. First of all, fading contributions are minimized communication system capable of near gigabit data rate has been by the spatial filtering effect of the antennas beamwidth, developed at IETR. The realized system covers 2 GHz available resulting in a higher coherence time. As shown in , when bandwidth. This paper describes the design and realization of the using directional antennas, the minimum observed coherence overall system including the baseband (BB), intermediate time was 32 ms (people walking at a speed of 1.7 m/s) which frequency (IF) and radiofrequency (RF) blocks. A differential is much higher than the lower limit of 1 ms (omnidirectionnal binary shift keying (DBPSK) modulation and a differential antennas). Then, the channel is considered invariant during the demodulation are adopted at IF. In the BB processing block, an coherence time and can be estimated once per few thousands original byte/frame synchronization technique is designed to of data symbols for Gbps transmission rate. Thus, the Doppler provide a small value of the preamble false alarm and missing effect (particularly due to the moving person) depends on the probabilities. For the system performances, two different real antenna beamwidth but it is not considered critical in indoor scenarios are investigated: measurements carried out in a large environments. The use of directional antennas also yield the gym and in hallways. Bit error rate (BER) measurements have benefits of reducing the number of multipath components (the been performed in different configurations: with/without RS (255, channel frequency selectivity) and therefore to simplify the 239) coding, with frame synchronization using 32/64 bits signal processing. As stated in , , the root mean square preambles. As shown by simulation, the 64 bits preamble (RMS) delay spread caused by multipath fading can be provides sufficient robustness and improves the system reduced to about 1 ns (the symbol duration for 1 Gbps with performance in term of BER. At a data rate of 875 Mbps, a BER -8BPSK modulation). This means that the channel coherence of 10 was measured at 30 m using high gain antennas for line-
of-sight (LOS) conditions. = 0.063/τ = 630 MHz bandwidth can be given as Bcoh, 0.9rmswhen using high gain antennas. In addition to a simple
differential demodulation (which offers higher tolerance to the Keywords-Millimeter-wave system; WPAN; single carrier; BER;
byte and frame synchronization inter-symbol interference (ISI) than others SC modulations),
the throughput less than 1 Gbps can be easily achieved I. INTRODUCTION without equalization. As the 60 GHz radio link operates only
in a single room configuration, an additional Radio over Fibre 60 GHZ wireless systems, currently under standardization (RoF) link is used to ensure the communications in all the within the unlicensed 57-66 GHz band, are aiming several rooms of a residential environment. For this reason, in this gigabits data rate for wireless personal area networks (WPANs) paper, we propose a hybrid optical/wireless system for the applications -. For any wireless system design, the indoor gigabit WPANs. The first system application in a selection of a modulation scheme is a main consideration and point-to-point configuration is the high-speed file transfer. has a large impact on the system complexity. In fact, problems Due to the cost of the transmission of the 60 GHz signals over such as power amplifier (PA) non-linearity and oscillator RoF, it is reasonable to transmit signals over the fiber at IF. phase noise are more important for these RF circuits resulting This paper is organized as follows. Section II describes the in performance degradation. These effects should be taken into transmitter (Tx) and the receiver (Rx). In this section, the account in the overall communication system. It was shown in baseband, the intermediate frequency and radiofrequency  that single carrier (SC) transmission has a lower tolerance blocks are presented. In Section III, measurement results are to phase noise and more resistant power PA non linearity than presented; this section represents the core contribution of the the multicarrier OFDM. Owing to these advantages, the paper. Section IV concludes the work. authors in  proposed the single carrier (SC) transmission for
multi-gigabit 60 GHz WPAN systems as defined in IEEE
II. TRANSMITTER AND RECEIVER DESIGN 802.15.3C standard. Up to now, in the literature, several
studies have considered propagation measurements , , Fig. 1 and Fig. 2 show the block diagram of the Tx and Rx potential applications, circuit design issues and several respectively. The multimedia data are transmitted from the modulations at 60 GHz -. However, few efforts have source (video server) through the G.E. interface of the 60 GHz been dedicated to the realization of a 60 GHz wireless system wireless transmitter. and its performance in a realistic environment.
Due to the high path loss at 60 GHz and the transmission
power restrictions, a simple solution is to use directional, high
This work is a part of Techim@ges research project supported by French “Media and Networks Cluster”, Comidom and Palmyre II projects financed by the “Region Bretagne”.
DML:Directly Modulated Laser (VCSEL)risk of packet loss since the source is always faster than the O/E:Optoelectronic converter (PIN photodiode )destination. In order to avoid the packet loss, a programmable DML logic circuit is used. The input byte stream is written into the O/E dual port FIFO memory (FPGA) at a high frequency 125 MHz. Source dataPattern ChannelPHY Preamble/The FIFO memory has been set up with two thresholds. When GeneratordataRS (255,239) encoder/the upper threshold is attained, the dual PHY block (controlled Scrambler/Differential encoder1.61 GHzRF 60 GHz by the FPGA) sends a „signal stop‟ (to the multimedia source) 8 807.43 MHz109.37 MHz reads out in order to stop the byte transfer. A slow frequency f100.92 MHz 1IF 3.5 GHz : 4X 3Multimedia sourceF2continuously the data stored in the FIFO. When the lower PLO 18.83 GHz PLO 3.5 GHz threshold is attained, the dual PHY block sends a „signal start‟ Gigabit Ethernet Clock managerinterface Txto launch a new Ethernet frame. Therefore, whatever the 70 MHz activity on the Ethernet access, the throughput at the output of 807.43 MHz the G.E. interface is constant. Then, the byte stream from the Files/Video serverG.E. interface is transferred in the BB-Tx, as shown in Fig. 4.
Figure 1. 60 GHz wireless Gigabit Ethernet transmitter FPGA Xilinx Virtex 4 TxSelect8RS (255,239)IF_TxPattern 8EncoderS/PIF 3.5 GHz 88generatorDual port88AGCDifferential 8ScramblerP/S FIFO memory8Encoder807.43 MbpsTsRF 60 GHz 875 MbpsEncoding X 3G.E. ControlinterfaceClockClock and data 70 MHz Clock managerfrecoveryf12109.37 MHz Channel 100.92 MHz 239 bytes239 bytes82391623916239816239168510807.43 MHz PLO 18.83 GHz Dataf= 100.928 MHz (source byte frequency) 1f= 109.375 MHz (channel byte frequency)2Synchro/ Descrambler/8 Gigabit Ethernet File transfer/RS (255, 239) decoderinterface Rxvideos streaming Figure 4. Transmitter baseband architecture (BB-Tx) Source data1.61 GHz BER A known pseudorandom sequence of 63 bits is completed Analyzer807.43 MHz with one more bit to obtain an 8 bytes preamble. This preamble
is sent at the beginning of each frame to achieve good frame
synchronization at the receiver. Due to the byte operation of RS Figure 2. 60 GHz wireless Gigabit Ethernet receiver coding, two clock frequencies f and f are used: 12The transmitted signal must contain timing information that FF (1) 12allows the clock recovery and the byte/frame synchronization f = = 100.929 MHz, f = = 109.375 MHz.1288at the receiver (Rx) . Thus, scrambling and preamble must 3.5 GHz2*239where: be considered. A differential encoder allows removing the F = = 875 MHz and F = F. 21242*(239+16)+8phase ambiguity at the Rx (by a differential demodulator).
As shown in Fig. 1, F is obtained from the IF. 2A. Transmitter design The frame format is realized as follows: the input source The Tx-G.E. interface is used to connect a home server to a byte stream is written into the dual port FIFO memory at a wireless link with about 800 Mbps bit rate, as shown in Fig. 3. slow frequency f. When the FIFO memory is half-full, the 1A header is inserted in the Ethernet frame to locate the starting encoding control reads out data stored in the register at a point of each received Ethernet frame at the receiver. higher frequency f. The encoding control generates an 8 bytes 2preamble at the beginning of each frame, which is bypassed by G.E-Tx interface 807.43 MHz/8the RS encoder and the scrambler. The RS encoder reads one GMIIFiles/ Video Rxbyte every clock period. After 239 clock periods, the encoding ServerData_validRJ45Txcontrol interrupts the bytes transfer during 16 clock periods, so J1FPGA Xilinx BB-TxDual Virtex 58DataIDE16 check bytes are added by the encoder. In all, two PHYXCV5LX20TRxRJ45successive data words of 239 bytes are coded before creating a ClockJ2TxFeedbacknew frame. After coding, the obtained data are scrambled link using an 8 bytes scrambling sequence. The scrambling
sequence is chosen in order to provide at the receiver the Figure 3. Transmitter Gigabit Ethernet interface lowest false detection of the preamble from the scrambled data.
Then, the obtained scrambled byte stream is differentially The gigabit media independent interface (GMII) is an interface encoded before the modulation. The differential encoder between the media access control (MAC) device and the PHY performs the delayed modulo-2 addition of the input data bit layer. The GMII is an 8-bit parallel interface synchronized at a (b) with the output bit (d): kkclock frequency of 125 MHz. However, this clock frequency is
different from the source byte frequency f = 807.43/8 =100.92 1 (2) d = db？k+1kkMHz generated by the clock manager in Fig. 1. Then, there is