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Authors’ draft of article published in
March/April 2004 QEX/Communications Quarterly
Please refer to http://www.qsl.net/ke5fx/synth.html for the latest updates and errata
A Versatile Hybrid Synthesizer for UHF/Microwave Projects
John Miles KE5FX
Richard Hosking VK6BRO
Ever want to build a “DC to daylight” receiver or digitally-controlled spectrum analyzer?
How about a transceiver for the Amateur UHF bands, or a signal generator with octave-band coverage? At the heart of each of these projects is a local oscillator with good stability and spectral purity. Our goal in this article is to present a versatile and practical synthesizer design
that can address almost any homebrewer‟s need for a digitally-tunable signal source from VHF to
Unlike most published approaches, we‟ve focused our design efforts as much on affordability, flexibility and reproducibility as on “specsmanship.” The synthesizer we‟ll describe offers continuous coverage between 1 and 2 GHz with fast switching time, sub-1 Hz tuning resoluion and very good close-in noise performance. There‟s nothing to tweak or align with exotic test equipment – if you build it, it will work. Best of all, every component is available off-the-shelf from Mini-Circuits, Digi-Key, and Analog Devices for a total of less than US $200.00!
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When it comes to modern synthesizer design trends, numerous authors have made the case for a hybrid topology that takes advantage of the combined strengths of direct digital
1,2,3,4,5synthesis (DDS) and traditional phase-locked loop technology. Before these hybrid
techniques became practical, PLL synthesis often involved awkward tradeoffs between frequency step size, freedom from spurious outputs, and overall loop complexity. While standalone DDS chips do not yet have the output frequency range (and in many cases, the spectral purity) to offer an across-the-board replacement for PLL technology, it‟s easy to use DDS technology to build a PLL synthesizer with arbitrary frequency-control precision, competitive spectral purity, and low overall complexity.
In its most basic form, a hybrid synthesizer uses a DDS source to provide a stable, clean, and precisely-tunable reference for a conventional PLL. The output of a hybrid synthesizer derives its tuning precision and stability from its DDS reference while providing the frequency coverage range typical of a PLL. The approach we‟ve taken is similar to that in Cornell Drentea,
6KW7CD‟s recent microwave DDS-driven PLL article, adapted to use newer, more readily-
available parts and improved post-DDS filtering. Tuning control is provided via the PC parallel port or an Atmel microcontroller. Like Cornell‟s design, our synthesizer can be used as a standalone VHF/UHF/microwave source or with an external frequency divider to achieve exceptional noise performance in HF applications.
The synthesizer‟s heart is the AD9852 DDS chip from Analog Devices. The AD9852 is used to generate a finely-tunable reference signal near 10.7 MHz for the PLL. Chosen for its superior performance over the less-costly (and somewhat more popular) 10-bit AD9850, the 12-bit AD9852 is clocked by either an onboard 10 MHz oscillator or an external 10 MHz source, using the chip‟s clock-multiplier feature to generate internal clock frequencies between 80 and 120 MHz.
After passing through a crystal filter to tame any wideband spurs, the signal from the DDS is amplified and converted to a square wave by an LT1016 comparator from Linear
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Technologies. The filtered and squared PLL reference signal from the comparator, along with a sample of the signal from the synthesizer‟s VCO obtained from a resistive divider, is applied to any of several programmable PLL synthesizer ICs from National Semiconductor‟s LMX2306/16/26 or Analog Devices‟ ADF4110/11/12/13 family. These PLL chips are marketed
toward the wireless- and cellular-communications industry, but their low prices, ease of use, and availability in small quantities make them attractive for Amateur Radio applications from the lower VHF region to frequencies well beyond the 2.4 GHz band.
Generation of the synthesizer‟s output signal is handled by a commercial varactor-tuned
voltage-controlled oscillator module. A wide variety of prepackaged VCOs are available with industry-standard PC board footprints from vendors such as Mini-Circuits and Synergy Microwave, offering various tuning ranges, output power levels, harmonic and noise performance specifications, and supply voltages. The synthesizer project described here uses the ROS-
2150VW from Mini-Circuits, which provides an impressive 970-2150 MHz tuning range for about $30.
Overall loop characteristics such as phase margin, bandwidth, and lockup time are determined by a third-order active loop filter based on the low-noise OPA27 opamp from Texas
Instruments. The opamp not only filters the digital signal from the PLL chip‟s charge-pump output,
but also amplifies it to the 0.5 - 25V level required to make the most of the VCO‟s tuning range.
Following the VCO and resistive divider, a GALI-5 MMIC from Mini-Circuits provides
approximately 16 dB of gain. With the ROS-2150VW VCO and divider as shown, power available at the output jack at mid-band is approximately +14 dBm with less than +/- 2 dB of variation between 1000 and 1800 MHz.
A key specification of any PLL frequency synthesizer is the spectral purity of its output signal. Phase noise, also known as “jitter,” is caused by random short-term excursions in the
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carrier‟s phase and can arise from a variety of causes. Amplitude noise is the other aspect of
composite noise performance as observed with a receiver or spectrum analyzer, but it is usually insignificant compared to phase/frequency jitter. Finally, in addition to composite AM/PM noise, the synthesizer‟s output signal may also contain discrete spurs that appear as sidebands on either or both sides of the carrier. For a detailed discussion of the nuances of noise and spur performance, see Dean Banerjee‟s outstanding PLL Performance, Simulation, and Design,
downloadable at http://www.national.com/appinfo/wireless/files/DeansBook_4_01.pdf. (A printed and bound version of Banerjee‟s book is also available at http://www.amazon.com.)
Unlike a simple LC oscillator stage, the factors that can contribute to noisy or otherwise-impure signals at the output of a PLL are almost too numerous to count. Worse, it‟s impossible to label a given synthesizer with a simple “spectral purity” specification that will allow direct comparisons with its peers. Noise and spurs are two-dimensional quantities – to evaluate their
severity, we must consider both the amplitude relative to the carrier signal and the frequency
offset from the carrier at which the effect in question was measured. Any synthesizer which will be used in a receiver or transmitter must be carefully designed to minimize noise and spurs at frequency offsets which have the potential to degrade the receiver or transmitter’s performance.
The last point is significant - a synthesizer serving as a wideband FM receiver‟s local oscillator can be designed to much looser specifications than one intended for use in a 40-meter contest-grade rig.
A detailed discussion of noise causes and cures is beyond the scope of this article. However, in a nutshell, PLL noise and spurious signal analysis must consider reference noise,
VCO noise, and the multiplication effect of the loop. The design of the loop filter is critical, as
the bandwidth of the loop should be tailored to the VCO‟s needs. It is also important to consider extraneous noise-and-spur sources such as power supplies and intermodulation effects
between various parts of the circuit.
Loop Multiplication Effect
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Any phase-locked loop will increase the phase-noise amplitude of its reference source by 20 * log(N) dB within the loop bandwidth, where N is the loop‟s overall frequency-multiplication
factor. Any discrete reference spurs within the loop bandwidth will also be amplified by a similar factor, noting that their frequency offset from the output carrier will remain the same as their offset from the reference. Consider a synthesizer with a 1-GHz output frequency and a 3-kHz loop bandwidth, whose reference frequency is 1 MHz with discrete sidebands at +/- 1 KHz and –80
dBc. N is 1000 in this case, and 20 * log(N) is 60 dB. At its output, the synthesizer will show
sidebands at +/- 1 KHz and –20 dBc, which may not be acceptable for many applications. It is
therefore critical to use a high-quality reference source for microwave PLLs with their high N
ratios -- or, failing that, a very narrow loop bandwidth with a high-quality VCO.
Reference-Related Noise and Spurs
The random phase-noise performance of a DDS is quite good. It is determined by either the noise of its own reference - typically a very clean crystal oscillator - or the noise-floor limitations of the VLSI process by which the DDS chip was fabricated (typically –140 dBc/Hz for
ECL technology and –150 dBc/Hz or better for modern CMOS parts such as the AD9852).
However, while its phase-noise performance is adequate for most purposes, the output of a DDS exhibits discrete sideband spurs due to phase truncation and timing tolerances in the lookup table and DAC. These are often significant enough to rule out the use of a standalone DDS as the first local oscillator in a high-performance HF receiver. Discrete spurs in the DDS reference can appear in the synthesizer‟s output signal at significant carrier offsets, falling away outside the loop
bandwidth after being amplified by 20 * log(N) dB within the loop bandwidth (see above).
In reality, our loop‟s vulnerability to spurs in its reference source is greater than one might expect. Both the National Semiconductor LMX2326 and Analog Devices ADF4112 PLL chips exhibit a readily-observed (yet apparently undocumented) tendency to respond to reference-signal spurs at offset intervals corresponding to their internal comparison frequency, from DC to 100 MHz and beyond. Consider a loop with a 1 MHz comparison frequency, achieved by programming the PLL chip for a reference-divider modulus (R) of 10 with a DDS-generated
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reference signal at 10 MHz. As expected, DDS spurs close to the 10 MHz reference will appear in the synthesizer‟s output signal as noted above. Additionally, any DDS spurs appearing near 1 MHz intervals on either side of the 10 MHz reference frequency will appear in the output signal exactly as if they had been generated in the vicinity of 10 MHz. For example, a spur at 7.001 MHz
would produce sidebands at +/- 1 KHz from the carrier at the output of the synthesizer. This effect has been noted with the National chip‟s reference/evaluation board as well as our prototype ADF4112-based synthesizer. It is clear that low-pass filtering the DDS reference is not enough –
we must bandpass-filter it to suppress as many spurs as possible across the entire RF spectrum.
Our synthesizer addresses DDS spur problems by severely band-limiting the loop‟s
reference signal with an inexpensive 4-pole monolithic crystal filter. With this 15-kHz-wide filter in place, a series of 5,000 automated measurements taken at randomly-selected frequencies between 1000 and 1800 MHz revealed no significant spurious responses at any frequency. Without the filter, the synthesizer‟s overall spur performance was dramatically worse. In the latter test, almost every randomly chosen frequency exhibited at least one noticeable spur.
The Loop Filter and VCO
The loop filter in a PLL is designed to attenuate high-frequency components of the loop error signal so that they do not modulate the VCO output. In practice, the loop filter cutoff is commonly set at between 2 and 5% of the reference frequency to obtain adequate attenuation of comparison-frequency sidebands appearing at the phase detector‟s output. In our circuit the comparison frequency is approximately 900 kHz, so this issue can be largely ignored. We consequently design the loop filter for best system phase-noise performance based on the VCO‟s
own noise characteristics.
At offsets from the VCO carrier less than the loop filter bandwidth, the PLL attenuates noise contributed by the VCO. At offsets that are significantly greater than the PLL‟s loop bandwidth, the principal source of noise is the VCO itself. Within the loop bandwidth, the noise performance is determined by the PLL reference source and the phase detector, and possibly the broadband noise floor of the frequency dividers as well. Even the noisiest VCO can be cleaned
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up by a PLL within its loop bandwidth, but extremely wide loop bandwidths carry a price of their
ADF4110/11/12/13, the inband noise own. As described in Analog Devices‟ data sheet for the
floor of a typical inexpensive phase-frequency detector is limited to –85 to –90 dBc/Hz, after
allowing for the multiplication effect of the loop as mentioned above. The phase-noise specifications of a good-quality VCO at offsets greater than 10 kHz from the carrier will be better than this -- typically around –95 to –110 dBc/Hz. Consequently, it makes sense to choose a loop
bandwidth narrower than the carrier-offset points where the VCO‟s free-running noise profile
crosses the PLL‟s own noise floor.
Besides requiring physically larger components, a narrower-than-necessary loop bandwidth allows more VCO noise to appear in the output signal. It also slows the loop lock time. The latter may be an issue where rapid tuning is required, such as in a sweep generator or spectrum analyzer application. Conversely, an excessively-wide loop bandwidth means that the PLL is actually contributing noise to the output, degrading the VCO‟s noise profile rather than improving it.
With the Mini-Circuits VCO family we‟ve spec<