5. Power states
This clause details how power states are used in UPF.
Note required: Just because a state is named ―on‖ or ―off‖ does not give it semantic meaning.
Note required: Negating a state in a Boolean expression evaluates to True whenever the
conditions of the state do not exist. Negating a state does not imply any other particular state is True. For example, if two states are defined on a supply set and they are named ―on‖ and ―off‖, ―! on‖ does not imply ―off‖ because ―! on‖ includes conditions that are
not included in the definitions of ―on‖ or ―off.‖
Supply nets, supply ports, supply sets and power domains have power states. The definition of the power state of each object is different.
5.1.1 Power states of supply nets and ports
Supply nets and ports form the foundation of the power specification. Each supply port and net maintains two pieces of information: a supply state and a voltage value, which together constitute the power state of the supply net or port. The power state information for supply nets and ports is defined by the supply_net_type; the state of being
FULL_ON, OFF, PARTIAL_ON, or UNDETERMINED and the voltage level (which
is relevant only for the FULL_ON and PARTIAL_ON states). A supply net may be
included in a supply set. Each supply set has a reference ground. The default reference ground for a supply set is an implicit common ground of 0 volts. The default reference ground can be explicitly overridden by specifying a supply net that is used as the reference ground for every supply net in the set. The voltage value of the supply net is in reference to this ground within the context of a supply set.
5.1.2 Power states of supply sets
Continuing up from the foundation of supply nets, the next step in defining the supply network is the supply set – a collection of supply nets that together define a complete
power supply. The supply set is composed of two or more supply nets. Therefore, the
power state for a supply set is specified in terms of the supply nets that compose the set. It is the combined states of the constituent supply net which determine if there is a current powering an element and the voltage level of the supply.
Supply sets can have special semantics in UPF, which are applied when the set is implicitly connected (see section 4.5.1) to provide power to design elements. The implicit connection semantics include simulation behavior semantics (simstate) that are specified
for the power state. The simstate is a specification at a digital level of abstraction of the ability of the supply set's power level to support a level of operational capability. The following simstates are defined:
a) NORMAL—The power level of the supply set is sufficient to support full and
complete operational (switching) capabilities with characterized timing.
b) CORRUPT—The power level of the supply set is either off (one or more supply
nets in the set are switched off terminating the flow of current) or at such a low
level that it cannot support switching and the retention of the state of transistors
cannot be guaranteed to be maintained even in the absence of changes or activity
in the elements powered by the supply.
c) CORRUPT_ON_ACTIVITY—The power level of the supply set is insufficient
to support switching operation with characterized timing. However, the power
level is sufficient that transistors retain their state as long as there is no switching
activity within the elements connected to the supply.
d) CORRUPT_SEQ_ON_CHANGE—The power level of the supply set is
insufficient to support switching operation in registers should the register inputs
change. The registers are insensitive to activity (non toggling glitches) on the data
and control inputs. However, the power level is sufficient to support the switching
operation of combinatorial logic with characterized timing.
e) CORRUPT_SEQ_ON_ACTIVITY—The power level of the supply set is
insufficient to support switching operation in registers if the data inputs of the
register are active. However, the power level is sufficient to support the switching
operation of combinatorial logic with characterized timing.
The simstate specification provides digital-simulation tools sufficient information for approximating the power-related behavior of logic implicitly connected to the supply set with sufficient accuracy.
NOTE—When greater accuracy is desired or required, a mixed signal or full analog simulation must be used. Since analog simulations already incorporate power, this format provides no additional semantics for analog verification.
Simulation results reflect the implemented hardware results only to the extent the UPF simstate specification for a given power state of a supply set is correctly specified. For example, if verification is performed with simulation of a supply set in a power state specified as having a CORRUPT_ON_ACTIVITY simstate, but the implementation is
more accurately classified as CORRUPT_SEQ_ON_CHANGE, the simulation results
NOTE--In the case above, the inaccuracy in simstate specification is conservative relative to the implemented hardware behavior. However, inaccurate specifications can be optimistic resulting in errors in the implemented hardware that simulation failed to expose.
Due to the laws of physics, a supply set shall be CORRUPT when any of the supply sets
which create the electric circuit powering elements is switched off (the circuit is open and not closed). Therefore, it shall be an error if a simstate other than CORRUPT is
associated with a supply set state in which the net_state of any supply net in the set is
220.127.116.11 Specification of min, nom, max voltage levels
Since the power state of a supply net or port is the current supply net value, specification of the min, nom, and max voltage levels cannot be made at the supply net- or port-level. The appropriate place to specify the min, nom, and max voltage levels is in a supply set's power state specification (see xxx).
5.1.3 Power states of power domains
The power state of a domain is determined by the state of supply sets associated with the domain. For example, the definition of a domain's MY_DOMAIN_IS_ON power state would logically require that the primary supply set be in a NORMAL simstate (all supply
nets of the primary supply set are on and the current delivered by the power circuit sufficient to support normal operation. Similarly, a SLEEP mode for the domain may require the primary to be in a CORRUPT state while appropriate retention and isolations
supplies are NORMAL.
Unlike supply nets, supply ports, and supply sets, power domains are composed of logic elements as well as power elements. Thus, the state of logic elements may be a relevant aspect to the specification of a domain's power state, e.g.,
a) A power domain is considered to be "On" when:
1) The logic signal controlling the power switch(es) for the domain's primary
supply set is active (the power switch is closed or on).
2) The logic signal(s) enabling isolation or triggering retention save or
restore are inactive.
b) A power domain is considered to be "Off" when:
1) The logic signal controlling the power switch(es) for the domain's primary
supply set is inactive (the power switch is open or off).
2) If the isolation or retention supplies are switched, the control signals for
those supplies are active (the power switch is on).
3) The clock line(s) are gated
4) The isolation enable(s) are active.
In fact, prior to having the golden source (the HDL and UPF source used as input to implementation tools), the design specification might not have a completely defined supply network, but it may have a power management block and associated power control signals which will turn power switches on/off, enable/disable isolation, etc. when fully specified. At this stage of design specification, the power domain's power states might only be defined in terms of the state of logic elements. The state of the domain's supply sets will be added later and is necessary for a complete supply network specification. Through support of incremental refinement of the power state specification, early power-aware simulations can be performed with only the logic net expressions defining the states with those logic expressions transitioning to assertions to be verified in later stages when the complete power state definition can be specified.
18.104.22.168 Power states of systems and subsystems
What constitutes a system is contextual. In one context, a system may be considered as complete by itself, e.g., one chip of a multi-chip or multi-board low power system. Although it might seem reasonable to define a "system" as that which is automatically implemented, UPF is not limited to that context and the verification of an entire system composed of multiple chips each with its own power design specification, as well as an overall power design specification for the board on which the chips are placed, needs to be supported. The power states of a system or subsystem are attributed on a design element. The use of the term system includes the term subsystem.
As all elements of a design must be in a power domain, specification of power states for a system or subsystem are attributed to the power domain(s) that are defined for the (sub)system. As a system power state may depend on the state of more than one power domain, the power state specification for a power domain may include references to the states of domains defined on scopes in the logic hierarchy that are descendents of the ―higher level‖ power domain. (Here, ―higher level‖ refers to the location of the power domain’s scope being closer to the design’s top-level root design element relative to the
scope of another power domain.) Therefore, UPF allows the power state for a power domain to reference the power state of any power domain whose scope is in the descendent tree of the scope of the domain.
Assuming that the domain CORE_PD is defined on the root scope of a processor design, the power states of CORE_PD can reference lower level power domains such as CACHE_PD, ALU_PD and FP_PD in the specification of its power states. Thus, an example power state of FULL_OP for CORE_PD would reasonably require that its primary supply set is in a NORMAL simstate (all supply nets of the primary supply set are on and the voltage of the supply is sufficient for normal operations) and that the CACHE_PD, ALU_PD and FP_PD are all in an equivalent FULL_OP mode. In contrast, a NON_FP_OP mode for the CORE_PD may be defined identically to FULL_OP except that the FP_PD may be in a SLEEP mode. By allowing a higher level domain to reference lower level domain’s power states in the specification of its own power states, subsystem and system power states can be defined in UPF.
The power state information defined for the top level power domain provides the guidance implementation tools need to optimize according to power state requirements. Consequently, the power states of the system shall define all the legal states of the system. Since it is not possible to check for completeness of the system power state specification, an implementation can only be optimized based on the power states that are defined. As stated previously, implementation tools shall only consider the supply net expressions in power state definitions. The supply net expressions are specified directly in the case of power states of supply sets or indirectly by reference to the power state of supply sets for a domain’s power states or the power states of other domains (which reference the power states of supply sets).
NOTE—Although the prototypical, top-down specification of power states suggests a power domain’s power states are defined in terms of the power states of supply sets and
lower level power domains, the power state of a domain can be specified entirely in terms of the state of supply sets and/or supply nets and supply ports; i.e., the hierarchical specification can be collapsed into a (relatively) flat power state specification. Top-down, hierarchical power state specification is convenient when the power design starts prior to the existence of the complete supply network and is refined into an implementation. The flat specification of power states of domains in terms of direct references to supply nets may be quicker and more concise when the power state specification is not captured until after the supply network is specified.
5.2 Power state name spaces
Power states are attributed to specific objects in the design. The power states can then be referenced by specifying the object_name.upf_state where object_name can be a
hierarchical name denoting a power domain, supply set or supply net. Power states are attributes of the object and can only be referenced via the object. Specifically, power
states of a domain are attributes of the domain and not attributes of the scope of the domain. Thus, a design element may be shared as the scope for multiple domains, each domain containing states with the same name (e.g., sleep) without incurring a name space collision.
The following objects may have power states attributed to them:
— Power domains
— Supply sets
— Supply nets (power state is not an attribute but the state – value -- of the net)
A power state shall be defined before it can be referenced. Semantically, the transition of an object from one power state to another is an event. The state of a supply net is
referenced as a SystemVerilog expression in the same manner that the state of a logic net is referenced. As the only other objects that have power states – supply sets and power
domains – are not objects that can otherwise be referenced in expressions, the power state of a supply set or power domain can be referenced in an expression simply through the supply set or power domain name. Examples:
supply_set_foo = SLEEP
-- Returns TRUE if supply_set_foo is in a state consistent with state SLEEP
ALU_PD != FULL_OP
-- Returns TRUE if the ALU_PD is in a state inconsistent with FULL_OP 5.3 Simulation semantics of a power state
The simulation semantics (simstate) corresponding to the current state of a supply set at
any given time shall be applied to all design elements implicitly connected to the primary supply. The simulation semantics are specified below.
This state is a normal, power-on functional state for all logic implicitly connected to the supply set. The simulator executes the design behavior consistent with the simulation
specification for the HDL(s) used to specify the design behavior or semantic of UPF created behavior (isolation, retention, level-shifting, etc.).
By default, the simstate of a supply set is in the NORMAL state only under the conditions specified in Table 3.
UPF does not define any meaning to the voltage level for determining the default NORMAL simulation semantic. All that is required is all supply nets of the set are FULL_ON.
Multiple supply set states can be defined with simstate == NORMAL.
This state is a power-on state that is not dynamically functional for all logic implicitly connected to the supply set. This state can be used to represent a high-voltage threshold, (body-bias) state that does not have characterized (defined) switching performance. In this power state, the current state of the logic implicitly connected to the supply set is maintained unless there is activity with any element. Upon activity on any element, then all elements implicitly connected to the supply set are corrupted.
There are no states of a supply set’s nets that, by default, are identified as simstate
having the value of CORRUPT_ON_ACTIVITY; i.e., this simulation behavioral
condition needs to be specified by an add_power_state command (see 7.5).
Multiple supply set states may be defined with simstate ==
This state is a power-off, non-functional state for all logic implicitly connected to the supply set. This state can be used to represent a power-gated/power-off supply set state. In this power state, the wires and registers within the implicitly connected logic are corrupted. The implicitly connected logic is disabled from evaluation while this state applies.
By default, simstate is in the CORRUPT state only under the conditions specified in
**Replace table references to UNKNOWN with UNDETERMINED
Multiple supply set states may be defined with simstate == CORRUPT.
This state is a power-on state that is not dynamically functional for registers implicitly connected to the supply set. Combinatorial logic functions normally and registers are corrupted when the register value is changed.
This state is a power-on state that is not dynamically functional for registers implicitly connected to the supply set. Combinatorial logic functions normally and registers are corrupted when the register is active.
This is a special, placeholder state. It allows early specification of a non-operational power state while deferring the detail of whether the supply set is actually switched off or in a non-operational bias mode. If the supply set is not refined to some other state, then simulations shall apply the semantics of CORRUPT for any supply set state that is NOT_NORMAL
5.4 Transitioning from one simstate state to another
In simulation, once it is detected a supply set has transitioned from one state to another the simulator shall check the simstate specification for that state and apply the
appropriate transitions (see 5.5.1 - 5.5.6).
If a supply set’s supply nets transition to states that are consistent with multiple power states—power states are not required to be exhaustively defined nor are they required to be mutually exclusive—then for each defined state with an simstate specification, the
simstate specifications shall be identical (i.e., it shall be an error if the specified simstate
values are not identical.
5.4.1 Any state to an unspecified simstate
Supply set power states need not specify a simstate state. If the simstate state is not
specified and the state does not match a default NORMAL or CORRUPT state, the
simstate of the immediately preceding supply set power state shall continue to be applied. 5.4.2 Any state transition to CORRUPT
In this case, the wires and registers driven by the logic implicitly connected to the supply set shall be corrupted. The processes modeling the logic that are implicitly connected to the supply set shall be disabled from being activated (evaluated).
5.4.3 Any state transition to CORRUPT_ON_ACTIVITY
In this case, the current state of wires and registers driven by the logic implicitly connected to the supply set shall remain unchanged at the transition. The processes modeling the logic that are implicitly connected to the supply set shall remain enabled for activation (evaluation). Any wire or register that is actively driven after transitioning to this state shall be corrupted.
Any attempt to restore a retention register’s retained value while in the
CORRUPT_ON_ACTIVITY state shall result in corruption of the register’s value.
5.4.4 Any state transition to CORRUPT_SEQ_ON_CHANGE
In this case, the current state of wires and registers driven by the logic implicitly connected to the supply set shall remain unchanged at the transition. The processes modeling the logic that are implicitly connected to the supply set shall be enabled for activation (evaluation). Changes to the register value after the transition result in the register value being corrupted.
Any attempt to restore a retention register’s retained value while in the
CORRUPT_SEQ_ON_CHANGE state shall result in corruption of the register’s value
if the restored value is different than the register’s current value.
5.4.5 Any state transition to CORRUPT_SEQ_ON_ACTIVITY
In this case, the current state of wires and registers driven by the logic implicitly connected to the supply set shall remain unchanged at the transition. The processes modeling the logic that are implicitly connected to the supply set shall be enabled for activation (evaluation). Any activity on the register after the transition shall result in the register value being corrupted.
Any attempt to restore a retention register’s retained value while in the CORRUPT_SEQ_ON_ACTIVITY state shall result in corruption of the register’s value.
5.4.6 Any state transition to NORMAL
In this case, the processes modeling the logic implicitly connected to the supply set shall be enabled for activation (evaluation). Combinatorial logic and inferred latches shall be evaluated. If any of a flip-flop’s level-sensitive control signals are active at the transition, the flip-flop shall be evaluated. A flip-flop register is not evaluated as long as its control signals are all inactive until the next active edge of its clock signal after the state transition.
5.4.7 Any state transition to NOT_NORMAL
NOT_NORMAL is simulated as though the simstate were specified as CORRUPT. 5.5 Power network initialization semantics
The initial state of supply ports and supply nets is UNDETERMINED. As all symbolic supply sets and supply nets map to an implicit, anonymous supply net, the state of the symbolic supplies are consistent with the implicit, anonymous supply net being initialized to the UNDETERMINED state.
5.6 Simulation initialization semantics
Simulation initialization semantics are defined by the corresponding HDL. Existing models rely on the HDL initialization semantics for operations such as initializing ROMs, etc. Therefore, UPF does not change the existing initialization semantics of HDLs. To model design power-up behavior, it is recommended that verification environments allow the simulation to initialize according to normal HDL semantics (as though the design is powered-on prior to the simulation initialization sequence). The verification environment
can, after initialization, power down the design and then take the design through the power-up sequencing.
5.7 Referencing and setting object power states from HDL code Power states cannot be set directly from within UPF as UPF does not model dynamic behavior. The power state of an object at any given time is determined by the state of the supply nets that (ultimately) define the power state of the object.
To support early verification of the power architecture of a system, UPF defines HDL routines that can be used to set the power state of an object. (Early verification is defined
as any point prior to the power specification being complete for implementation purposes.) These routines can be used in the testbench or verification environment and can also be used to create behavioral models of objects such as on-chip bias generators. To support general verification requirements, UPF provides HDL routines to get the current power state of an object. Changes in the object state generate an event which can activate HDL processes that are waiting on a change in the object’s state. See annex B
for more information on these routines.