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In submicron processes, signal delay due to interconnect

By Jon Long,2014-06-13 20:38
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In submicron processes, signal delay due to interconnect

    2007 IC/CAD Contest

    Problem B3;

    Interconnect Parasitic RC Extraction

    Source: Cadence Design Systems, Inc.

    1. Introduction

    In submicron processes, signal delay due to interconnect parasitics becomes much more significant than the contribution to signal delay due to the inherent cell delays. Approximately 80% of the delay for most paths is now due to interconnect delays. Therefore accurate modeling of the parasitics on the interconnects is vital for high performance chip designs. Also, signal integrity analysis requires accurate coupling capacitance extraction. However, accuracy of parasitic extraction comes at a cost in

    terms of run time for performing the extraction. It is a function of design size, process, desired results and the number and configurations of systems that are available to do the extraction. Meeting timing constraints and resolving all timing violations in designs below 0.13um can often take several iterations in the synthesis, placement, and routing loop. Hence an interconnect parasitic extraction tool needs to complete the process in short time period but with high accuracy.

Figure 1 shows a typical flow for cell-level parasitic extraction.

    Technology Process file Generation

    Tech File Design Layout

    RC Cell

    Extraction Library

    Cell Timing

    DSPF/SPEF Library

    Timing Analysis

    Figure 1. Cell-Level Parasitic Extraction

     1

2. Problem Description

    Given a design layout from the result of cell-based placement and routing tool, which contains the cell placement information, interconnect wires and vias that connect the I/O pins and instance pins, the program is required to extract the interconnect parasitic capacitances and resistances based on the provided process information and output the extracted results in DSPF (Detailed Standard Parasitic Format) file.

    The process information includes (1) the sheet resistance of each interconnect layer (2) the contact resistance of each via cell, and (3) the parasitic capacitance table for each interconnect layer.

    To simplify the parasitic resistance model, there is only one sheet resistance for each interconnect layer without considering the wire width and density effect. A resistance value is given for each basic via cell (including the via shape, the top-layer interconnect shape and the bottom-layer interconnect shape), e.g. a via shape with a metal2 shape and metal1 shape making the via1 cell. For example, the sheet resistance of metal1 is 0.07 Ω

    (ohm) per square; the sheet resistance of metal2 is 0.05 Ω per square; and the via1 cell’s

    resistance is 0.95Ω. Figure 2 shows how the parasitic resistance network is extracted for the interconnect wires.

    Neta:2 Neta 1.8umNeta:3 0.3umNeta mm mm

    R1 R3

    1.4umVia 1 cell mm R2

    Metal1

    R1 = 1.8/0.3 * 0.07 = 0.42 Ω

    R2 = 1.4/0.25 * 0.05 = 0.28 Ω Metal2

    R3 = 0.95 Ω Neta:4

    Figure 2 0.25um

    Then the parasitic resistance network of net “Neta” is represented in spice format as below,

    R1 Neta Neta:2 0.42

    R2 Neta:3 Neta:4 0.95

    R3 Neta:2 Neta:3 0.28

    Note, the split subnodes of the net are named as the netname (Neta) concatenated with the subnode delimiter (:) and a positive integer number, like Neta:2, Neta:3, etc.. If the subnode is connected to a pin instance, then the subnode name will be represented by the cell instance’s name concatenated with the demiliter (:) and its pin name. If Neta:4 is connected to cell instance I0, pinName A, then, R2 will become

    R2 Neta:3 I0:A 0.95

     2

    Where

    Metal1 I/O Pin

    Metal2 Cell instance

    via1 Instance pin

    Figure 3

A design layout is shown in Figure 3, below is the extracted networks for some of the

    nets, pin I1 connected to g1:A and pin O connected to g3:Y, represented in DSPF,

    R1_0 I1:2 I1 0.479875 metal2 R

    R2_0 I1:1 I1:2 0.950000 Via1 R

    R3_0 g1:A I1:1 0.655500 metal1 R

    R1_2 O:1 g3:Y 0.950000 Via1 R

    R2_2 O O:1 0.614625 metal2 R

     3

    To simplify the parasitic capacitance model, the parasitic capacitance effect of an interconnect shape contains three parts, the area capacitance (C) to substrate, the fringe a

    or side-wall capacitance (C) to substrate and cross-coupling capacitance (C) between fc

    the shape and its adjacent shapes on the same layer, as shown in Figure 4.

    CFigure 4 c C c

    CC ff

     Ca

    Substrate

    Here, we consider the overlap-capacitance between the interconnect layer to the substrate only and ignore intermediate layers between them, i.e. for a metal2 wire, we calculate the area and side-wall capacitance between the wire and substrate and the cross-coupling capacitance between the wire and its adjacent metal2 wires. It does not matter if there is metal1 wire underneath the metal2 wire.

    The three values are functions of the wire width and the spacing (distance) between the wire and its adjacencies, and are represented as a table. For example, the following is the capacitance table for metal1,

    Width (um) Spacing (um) C (fF/um) C(fF/um) C(fF/um) C(fF/um) totalc a f

    0.16 0.16 0.2467 0.0949 0.0303 0.0131

    0.16 0.2 0.2123 0.0747 0.0303 0.0162

    0.16 0.52 0.1434 0.02 0.0303 0.0365

    0.16 1.2 0.1365 0.0025 0.0303 0.0506

    0.16 2.0 0.1364 0.0003 0.0303 0.0527

    0.48 0.16 0.3114 0.0967 0.0909 0.0133

    0.48 0.2 0.2763 0.0761 0.0909 0.0164

    0.48 0.52 0.2054 0.0204 0.0909 0.0368

    0.48 1.2 0.1983 0.0025 0.0909 0.0511

    0.48 2.0 0.1982 0.0003 0.0909 0.0533

    Table 1. Capacitance Table for Interconnect Layer Metal1

If the width of the middle wire in the figure 4 is 0.16um and the distances between the

    wire to its adjacencies on left-hand and right-hand are both 0.2um, according to the table

    (the row with color highlighted), the fringe (side-wall) capacitances on both sides are 0.0162 fF/um, and the coupling capacitance to both adjacencies are 0.0747 fF/um each, the area capacitance of the middle wire is 0.0303 fF/um. And the total lumped capacitance of the middle wire equals to 0.0303 + 0.0747 * 2 + 0.0162 * 2 = 0.2123 fF/um. If the length of the wire is 10um, then its lumped capacitance value is 2.123fF.

     4

We can use interpolation method to calculate C, C, and C if the wire width and/or afc

    distance are not shown in the table.

    The following demonstrate a simple method to extract the parasitic capacitances of the interconnect shapes.

    13um

    0.2um C

     0.2um 5um

    0.52um 0.16um 11um A

    3.8um 0.16u6.2um

    m B 0.16um

    Figure 5 10um

In Figure 5, there are three metal1 wires (net A, B, C), according to the capacitance table

    shown in Table 1, the three parts of capacitance values for each net are calculated as shown in Table 2. Note, in calculating C and C, the wires’ sidewalls are split into fc

    several segments depending on it environment (the distance between its neighbors). For example, the sidewall capacitanceof the segment colored in yellow of Net A is calculated

    by its length, 6.2um, multiplying the C coefficient 0.0131 (mapped to the space value f

    0.16um); the sidewall capacitanceof the segment colored in purple of Net A is calculated

    by its length, 5.8um, multiplying the C coefficient 0.0527 (mapped to the largest space f

    value since it has no adjacency).

    Net A has the largest value of capacitance, then Net C, then Net B. Table 3 shows the cross-coupling capacitance between two nets.

     Net A Net B Net C

    0.0303 * 11 0.0303 * 10 (0.0303/0.16*0.2) * 13 C area

    0.0527 * 5.8 0.0527 * 10 0.0527 * 13 C f

     0.0131 * 6.2 0.0131 * 6.2 0.0527 * 4.2

     0.0527 * 6 0.0365 * 3.8 0.0365 * 3.8

     0.0162 * 5 0.0162 * 5

    0.0949 * 6.2 (A-B) 0.0949 * 6.2 (B-A) 0.0747 * 5 (C-A) C c

     0.0747 * 5 (A-C) 0.02 * 3.8 (B-C) 0.02 * 3.8 (C-B)

    2.07926 fF 1.7143 fF 2.068015 fF C total

    Table 2. Interconnect wire parasitic capacitance calculation for Figure 5

    A B C C c

    A - 0.58838 0.3735

    B 0.58838 - 0.076

    C 0.3735 0.076 -

    Table 3. Cross-Coupling Capacitance between different nets in Figure 5.

     5

3. Inputs

    There are three inputs to the program, two input files in text format and a number specifying how many critical nets are expected to be reported in the output.

    1. The technology file (techfile) containing the following process information,

    a. Interconnect layer sheet resistance, and its default wire width (MinWidth)

    b. Via cell resistance

    c. The nonDefault rule(s) defining the wiring width for the specified

    nondefault rule name which could be referenced in the NETS session of

    DEF file. The total number of non-default rules is limited to 32. The

    default wire width is the minimum wire width defined in session a.

    d. Capacitance table for each interconnect layer

    2. Design data in Design Exchange Format containing

    ; DESIGN

    ; UNIT DISTANCE

    ; NETS

    3. Number of critical nets need to be reported in output file:

    It is a positive integer, minimum is 1, and maximum is the total net count of the

    design input.

; Techfile format

[LAYER interconnectLayerName

     MinWidth minWidth

    Resistance sheetResistanceValue

    END]…

[VIA viaLayerName

     TopLayer topInterconnectLayerName

     BottomLayer bottomInterconnectLayerName

     Resistance viaResistanceValue

    END]…

[NONDEFAULTRULE ruleName

    {LAYER LayerName

     WIDTH width ;

     END layerName} …

     END ruleName] …

BASIC_CAP_TABLE

    [interConnectLayerName

    width(um) space(um) Ctot(Ff/um) Cc(Ff/um) Carea(Ff/um) Cfrg(Ff/um) [floatingPoint floatingPoint floatingPoint floatingPoint floatingPoint floatingPoint] …

    ]…

    ; Design Data in Design Exchange Format (DEF)

     6

    Standard DEF files can contain the following statements and sections. The

    statements and sections are in the following order.

    VERSION statement

    NAMESCASESENSITIVE statement

    DIVIDERCHAR statement

    BUSBITCHARS statement

    DESIGN statement

    [ TECHNOLOGY statement ]

    [ UNITS statement ]

    [ HISTORY statement ] ...

    [ PROPERTYDEFINITIONS section ]

    [ DIEAREA statement ]

    [ ROWS statement ] ...

    [ TRACKS statement ] ...

    [ GCELLGRID statement ] ...

    [ VIAS statement ]

    [ REGIONS statement ]

    COMPONENTS section

    [ PINS section ]

    [ PINPROPERTIES section ]

    [ BLOCKAGES section ]

    [ SLOTS section ]

    [ FILLS section ]

    [ SPECIALNETS section ]

    NETS section

    [ SCANCHAINS section ]

    [ GROUPS section ]

    [ BEGINEXT section ] ...

    END DESIGN statement

     Only part of the sections needs to be read in for doing the RC extraction,

    especially the NETS section.

4. Outputs

Two output files are expected,

    1. The total lumped capacitance and parasitic R network in DSPF format for

    the top N critical nets (non power/ground nets) which have most serious

    lumped capacitance values

    2. The cross coupling capacitance values of the top N critical nets which

    have biggest net-to-net capacitance values, where N is specified in the input.

The program (executable) must be called “rcx”, when excuted, the techfile, design data

    file and numberOfCriticalNets will be specified as its arguments, i.e.

    rcx techFileName designFileName numberOfCriticalNets

    The program should generate two output files, called design.dspf and design.netcap,

    where design is the design name specified in the design date file.

     7

5. Example

Following is an example showing you the inputs data and desired output.

A design with three interconnect (metal) layers, the parasitic RC for the most 4 critical

    nets (all of the nets) are required to be reported in output; i.e. executing

    rcx tech.file test2.def 4

; The input Techfile called “tech.file”

LAYER M1

     MinWidth 0.16000 Resistance 0.07700 END

    LAYER M2

    MinWidth 0.20000

     Resistance 0.05500 END

    LAYER M3

    MinWidth 0.20000

     Resistance 0.05500 END

    VIA VIA_1

     TopLayer M2

     BottomLayer M1

     Resistance 0.95000 END

    VIA VIA_2

     TopLayer M3

     BottomLayer M2

     Resistance 0.95000 END

    NONDEFAULTRULE wide2x

     LAYER M1

     WIDTH 0.32;

     END M1

     LAYER M2

     WIDTH 0.4;

     END M2

     LAYER M3

     WIDTH 0.4;

     END M3

    END wide2x

    NONDEFAULTRULE wide5x

     LAYER M1

     WIDTH 0.8;

     END M1

     LAYER M2

     WIDTH 1.0;

     END M2

     LAYER M3

     WIDTH 1.0;

     8

     END M3

    END wide5x

BASIC_CAP_TABLE ...

    M1

    width(um) space(um) Ctot(Ff/um) Cc(Ff/um) Carea(Ff/um) Cfrg(Ff/um) 0.160 0.180 0.2123 0.0747 0.0303 0.0162 0.160 0.520 0.1434 0.0200 0.0303 0.0365 0.160 1.200 0.1365 0.0025 0.0303 0.0506 0.160 2.220 0.1363 0.0001 0.0303 0.0529 0.480 0.180 0.2763 0.0761 0.0909 0.0164 0.480 0.520 0.2054 0.0204 0.0909 0.0368 0.480 1.200 0.1983 0.0025 0.0909 0.0511 0.480 2.220 0.1982 0.0001 0.0909 0.0535 1.000 0.180 0.3750 0.0762 0.1894 0.0164 1.000 0.520 0.3040 0.0204 0.1894 0.0369 1.000 1.200 0.2969 0.0025 0.1894 0.0512 1.000 2.220 0.2967 0.0001 0.1894 0.0535

M2

    width(um) space(um) Ctot(Ff/um) Cc(Ff/um) Carea(Ff/um) Cfrg(Ff/um) 0.200 0.210 0.1747 0.0625 0.0245 0.0124 0.200 0.620 0.1156 0.0166 0.0245 0.0289 0.200 1.440 0.1098 0.0020 0.0245 0.0406 0.200 2.670 0.1097 0.0001 0.0245 0.0425 0.600 0.210 0.2264 0.0636 0.0734 0.0127 0.600 0.620 0.1659 0.0169 0.0734 0.0293 0.600 1.440 0.1599 0.0021 0.0734 0.0411 0.600 2.670 0.1598 0.0001 0.0734 0.0431 1.200 0.210 0.3004 0.0637 0.1468 0.0129 1.200 0.620 0.2397 0.0169 0.1468 0.0295 1.200 1.440 0.2337 0.0021 0.1468 0.0414 1.200 2.670 0.2336 0.0001 0.1468 0.0433

M3

    width(um) space(um) Ctot(Ff/um) Cc(Ff/um) Carea(Ff/um) Cfrg(Ff/um) 0.200 0.210 0.1747 0.0625 0.0245 0.0124 0.200 0.620 0.1156 0.0166 0.0245 0.0289 0.200 1.440 0.1098 0.0020 0.0245 0.0406 0.200 2.670 0.1097 0.0001 0.0245 0.0425 0.600 0.210 0.2264 0.0636 0.0734 0.0127 0.600 0.620 0.1659 0.0169 0.0734 0.0293 0.600 1.440 0.1599 0.0021 0.0734 0.0411 0.600 2.670 0.1598 0.0001 0.0734 0.0431 1.200 0.210 0.3004 0.0637 0.1468 0.0129 1.200 0.620 0.2397 0.0169 0.1468 0.0295 1.200 1.440 0.2337 0.0021 0.1468 0.0414 1.200 2.670 0.2336 0.0001 0.1468 0.0433

    ; The input DEF file called test2.def (layout shown in Figure 3) DESIGN test2 ;

    UNITS DISTANCE MICRONS 1000 ;

    

    NETS 4 ;

    - I1

     9

     ( PIN I1 ) ( g1 A )

     + ROUTED METAL1 ( 3910 1845 ) ( 5290 * 0 )

     NEW METAL2 ( 3910 100 0 ) ( * 1845 ) VIA1 ; - I2

     ( PIN I2 ) ( g3 OE )

     + ROUTED METAL2 ( 690 1845 ) ( * 4305 ) VIA1

     NEW METAL1 ( 690 4305 ) ( 2990 * ) VIA1

     NEW METAL2 ( 2990 100 0 ) ( * 4305 )

     NEW METAL2 ( 690 1845 ) VIA1

     ;

    - O

     ( PIN O ) ( g3 Y )

     + ROUTED METAL2 ( 3450 2665 ) ( * 4900 0 )

     NEW METAL2 ( 3450 2665 ) VIA1

     ;

    - B1

     ( g3 A ) ( g1 Y )

     + ROUTED METAL2 ( 5750 2665 ) ( * 4715 ) VIA1

     NEW METAL1 ( 2530 4715 ) ( 5750 * )

     NEW METAL2 ( 2530 1435 ) ( * 4715 ) VIA1

     NEW METAL2 ( 5750 2665 ) VIA1

     NEW METAL2 ( 2530 1435 ) VIA1

     ;

    END NETS

    ; The Output DSPF file (called test2.dspf)

    * RC extraction data for design test2 *

    *|DSPF 1.0

    *

    *|DELIMITER :

    *

    .SUBCKT test2

    + I1 I2 O

* Net Section

    *

    *

    *|GROUND_NET 0

    *

    *|NET I1 0.000400PF

    *|P (I1 I 0.000000PF 3.910 0.100) *|I (g1:A g1 A I 0.000000PF 5.290 1.845) *|S (I1:1 3.910 1.845)

    *|S (I1:2 3.910 1.845)

    C1_0 g1:A 0 0.000087PF

    C2_0 I1:1 0 0.000087PF

    C3_0 I1:2 0 0.000113PF

    C4_0 I1 0 0.000113PF

    R1_0 I1:2 I1 0.479875

    R2_0 I1:1 I1:2 0.950000

    R3_0 g1:A I1:1 0.655500

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