readme - Nios II Etherent Standard Design Example
This design is provided to showcase the Nios II Ethernet Standard design running
on Altera development boards and highlights many of the features of the Nios II
processor, Triple Speed Ethernet and the Scatter Gather DMA. The design is meant
to be simple and straight-forward.
To build the system, you will need to generate the system in SOPC Builder and
compile the design in Quartus.
For SW development, the .sopcinfo file and hardware image (.sof) are provided.
Contents of the System:
- Nios II/f Core
- JTAG Debug Module (Level 1)
- DDRx SDRAM Controller
- CFI Flash Memory Interface
- Ethernet Interface
- Descriptor memory (On Chip Memory)
- TSE MAC
- TX SGDMA
- RX SGDMA
- System Timer
- High Resolution Timer
- Performance Counter
- System ID Peripheral
- JTAG UART
- LED PIO
- Push Button PIO
Supported Software Examples:
- Blank Project
- Hello World
- Board Diagnostic
- Count Binary
- Hello Free-Standing
- Hello MicroC/OS II
- Hello World Small
- Memory Test
- Simple Sockets Server
- Web Server
Supported Development Boards:
- Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition (3C25)
- Embedded Systems Development Kit, Cyclone III Edition (3C120)
- Stratix IV GX FPGA Development Kit (4SGX230)
- The top level of this design is the HDL file generated around the SOPC Builder design.
This wrapper performs the following functions:
1.) Renaming the DDR-associated pins from SOPC Builder to match the timing assignments produced by the DDR megafunction.
2.) If you modify and regenerate the SOPC Builder design, the port list of the SOPC Builder instance may change.
You must manually edit the HDL wrapper file to rectify any discrepancies.
- This Quartus II project contains assignments that match the port names produced by SOPC Builder.
If you add or modify SOPC Builder components, the pin assignments may no longer be valid.
To view the Assignment Editor in the Quartus II software, in the Assignments menu, click "Assignment Editor".
- This design contains the DDR memory and Triple Speed Ethernet components. Any design containing these cores must be re-generated
in SOPC Builder before re-compiling it in Quartus if the installation path to the Altera toolchain has changed since it was
last generated. This is because these cores make use of RTL libraries that are referenced using absolute paths. The re-generation
process will update these absolute paths.
Attempting to recompile in Quartus II without regenerating will result in an error of the following form during Quartus II Analysis and
Error: Node instance "ddr_control" instantiates undefined entity "auk_ddr_controller"
- Only single bank DDR memory is used as program and data memory. Thus, memtest should not run on
the DDR memory bank as could cause destructive effect to the program code and data.
- For the Embedded Systems Development Kit, Cyclone II Edition, the LCD daughtercard's Ethernet
connection is used versus the on-board Ethernet Connection. This allows the software examples
to work automatically (the on-board Ethernet Connection uses RGMII which requires changes be
made to the software).