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JTAG HW Module Test Based on OpenOCD

By Bryan Hamilton,2014-12-08 18:59
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JTAG HW Module Test Based on OpenOCDHW,on,On,JTAG,Test,Based,based,test

    JTAG HW Module Test Based on OpenOCD

    1. Status and Control

    (1) arm core_state [‘arm’|’thumb’]

    Displays the core state, optionally changing it to process either ‘arm’ or ‘thumb’ instructions.

    (2) reg [( number|name) [value]]

    Access a single register by number or by its name. Through this command, it can be

    tested whether reading and writing ARM core registers can be implemented by JTAG. Some important ARM core registers, such as PC, CSDR, SP, can also be accessed through this command. This enables the ability to control and observe ARM core. (3) halt [ms]

    Send a halt request to the target. After successful implementation of this command, the ARM is halted with its state (ARM or THUMB), process mode and its CSPR, PC registers’ values displayed as response.

    (4) resume [address]

    Resume the halted ARM core at the current code position or jump into the optional address if it is provided.

    (5) step [address]

    This command resembles resume other than single-step the target at the current code position or the optional address

    (6) arm mcr pX op1 CRn CRm op2 value

    (7) arm mrc pX coproc op1 CRn CRm op2

    These two commands are specific to ARM coprocessor operations. Refer to ARM architecture spec. for ARM mcr/mrc instructions’ usage.

    2. Memory Access

    (1) mdw [phys] addr [count]

    (2) mdh [phys] addr [count]

    (3) mdb [phys] addr [count]

    Display contents of address addr, as 32-bit words (mdw), 16-bit halfwords (mdh), or 8-bit

    bytes (mdb). In practice, count should be specified as different values to test whether mass consecutive reading memory is stable.

    (4) mww [phys] addr [count]

    (5) mwh [phys] addr [count]

    (6) mwb [phys] addr [count]

    Writes the specified word (32 bits), halfword (16 bits), or byte (8-bit) value, at the specified address addr. Assign different values to count to test whether mass consecutive writing memory is stable.

    (7) load_image filename address [[‘bin’| ‘ihex’|‘elf ’|‘s19’] ‘min_addr’ ‘max_length’]

    Load image from file filename to target memory offset by address from its load address.

    The file format may optionally be specified (‘bin’, ‘ihex’, ‘elf ’, or ‘s19’).This command

    provides the capacity to load file from host to the target.

    3. ARMv7-Specific DAP Test

    (1) dap apid [num]

    (2) dap apsel [num]

    There are three kinds of APs, including MEM-AHB, MEM-APB, JTAG-AP. After switching to different AP through this command, memory access commands should be repeated to verify different AP access paths.

    (3) dap baseaddr [num]

    (4) dap info [num]

    (5) dap memaccess [num]

    4. GDB with JTAG

    (1) bp [address len [‘hw’]]

    With no parameters, lists all active breakpoints. Else sets a breakpoint on code execution

    starting at address for length bytes. This command tests whether ARM debug module is accessible through JTAG and whether its breakpoint functions properly. (2) rbp address

    Remove the breakpoint at the address.

    (3) rwp address

    Remove the watchpoint at the address.

    (4) wp [address len [(‘r’ | ‘w’ |’a’) [value [mask]]]]

    With no parameters, lists all active watchpoints. Else sets a data watchpoint on data from

    address for length bytes.

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