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ade_5_0.trans

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     Overhead Transparencies for

     Analog Design Environment

     Training Manual Version 5.0

     Education Services September 30, 2002

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     Module 1: Introduction to ADE 5.0

     Topics in this module

     s s s s s s s s s s s s

     Course objectives Course outline Class schedule Getting help, technical support, and documentation The Design Framework II Design Environment Accessing design tools Creating a library Creating cells and cell views Schematic capture Analog simulation Analyses Summary

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     Introduction to ADE 5.0

     1-3

     Course Objectives

     s s s s s s s s s s s

     Learn how to create schematics, symbols, and a design hierarchy Set up and run analog simulations Analyze simulation results Evaluate sensitivities and mismatches to improve circuit performance. Run Corners, Monte Carlo, and Optimization tools to improve yield Create and use OCEAN scripts and SKILL to set up and run simulations Understand the Component Description Format (CDF) Create configurations with the Hierarchy Editor (HED) Use subcircuits and macromodels Run the parasitic simulation flow Use advanced tools to solve special problems

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     Introduction to ADE 5.0

     1-5

     Course Outline

     1 2 3 4 5 6 7 8 9 10 11 Introduction to ADE 5.0 Schematic Entry Analog Simulation Simulation Results Display Tools Analyzing Simulation Results SKILL and OCEAN Parametric Analysis Corners Analysis Monte Carlo Analysis Optimization Analysis Circuit Surfer 14 15 16 17 12 13 Component Description Format (CDF) Macromodels, Subcircuits, and Inline Subcircuits Inherited Connections The Hierarchy Editor Overview of Parasitic Simulation Assura Parasitic Simulation Flow

     Appendixes: A Diva Parasitic Simulation Flow B WaveScan Display

    Tools C Spectre MDL D Match Analysis, dcmatch E Advanced Topics in ADE

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     Introduction to ADE 5.0

     1-7

     Class Schedule

     Day 1

     1 2 3 4 Introduction to ADE 5.0 Schematic Entry Analog Simulation Simulation Results Display Tools

     Day 3

     10 11 12 13 Optimization Analysis Circuit Surfer Component Description Format (CDF) Macromodels, Subcircuits, and Inline Subcircuits

     Day 2

     5 6 7 8 9 Analyzing Simulation Results SKILL and OCEAN Parametric Analysis Corners Analysis Monte Carlo Analysis

     Day 4

     14 Inherited Connections 15 The Hierarchy Editor 16 Overview of Parasitic Simulation 17 Assura Parasitic Simulation Flow Class Evaluations

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     Introduction to ADE 5.0

     1-9

     Getting Help

     You can get help with Cadence software from the following sources:

     s s s s s

     Help button on forms and windows Cadence online documentation (CDSDoc) Education Services training manuals SourceLink? online customer support Customer Response Center (CRC)

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     Introduction to ADE 5.0

     1-11

     Overview of Analog Design Environment

     Analog Design Environment is a software tool set within Design Framework II that is used to set up and run analog simulations. The Analog Design Environment also accesses and views the simulation results. The Analog Design Environment allows you to:

     s s s s s s s s s s

     Choose the simulator host Choose the type of analysis: ac, dc, transient, parametric, sensitivity, etc. Set design variables: Vdd, frequency, Cout, etc. Append model files and include files Netlist and run simulations Quickly alter the simulation setup and rerun the

    simulation Plot simulation results in the Waveform display tool Evaluate simulation results using waveform expressions Run multiple simulation tools: Corners, Monte Carlo, Optimizer, etc. Automatically set up, save, and run OCEAN scripts

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     Introduction to ADE 5.0

     1-13

     Design System Initialization Files

     Login icfb & icms & msfb &

     Operating System Environment

     Window System

     Design Framework II ( IC - 5.0 )

     Analog Design Environment, schematic capture tools, layout, and verification software.

     Window Manager

     .cshrc .login

     .cdsenv .cdsinit cds.lib

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     Introduction to ADE 5.0

     1-15

     Overview of the Design Framework II Environment

     Schematic Capture & Symbol Editor

     FrameworkSimulation Tools Mask Layout Setup Simulate Results

     Update Design

     Simulation Control, Simulation Results, Waveforms, and Expressions

     Schematic Editor

     Window Edit Schematic

     2

     Component Description

     The Framework

     Framework ToolsMask Layout Layout 3 Window Edit Mask Layout

     Layout Verification

     R:

     Parasitic Simulation and Backannotation Physical Design

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     5

     Introduction to ADE 5.0

     1-17

     Advantages of Using Design Framework II

     s

     Common software environment for using schematic capture, simulation,

    layout, and design verification Easy-to-learn, consistent user interface Similar appearance between most forms and windows Communication between software tools within the DFII environment Tool windows remain open while running other applications Data can be ??back annotated?? ?ª From layout to schematic ?ª From simulation to schematic ?ª From simulation to layout ?ª etc. Applications may be customized or automated using SKILL or the OCEAN command language

     s s s s s

     s

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     Introduction to ADE 5.0

     1-19

     The Command Interpreter Window (CIW)

     Enter: icfb &, icms &, or msfb &

     This Is Your Control Panel for DFII Applications!

     Pull down menus

     Output Area Text Field (Enter SKILL Commands)

     Prompt Line

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     Mouse Button Cues

     Introduction to ADE 5.0

     1-21

     Using a Form

     A Sample Form OK Cancel Defaults Apply Load Save Library Browser Run Directory Library Name Top Cell Name View Name Output File Output Show Messages Library Version 5.0 mux2 layout Stream DB ASCII Dump . classLib Help

     Template File

     Text entry area

     Toggle Button Cyclic Field

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     Radio Button

     Introduction to ADE 5.0

     1-23

     Initializing the Design Framework II Environment

     The Design Framework II software reads your .cdsinit file at startup to set up your environment. The .cdsinit file:

     s

     Sets user-defined bindkeys when the Design Framework II environment is started. Redefines system-wide defaults. Contains SKILL commands.

     s s

     The search order for the .cdsinit file is:

     s s s

     /tools/dfII/local the current directory the home directory

     Here is the path to a sample .cdsinit file:

     /tools/dfII/samples/artist/cdsinit

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     Introduction to ADE 5.0

     1-25

     IC Design Flow, Front to Back

     System Level Design:

     Product definition, System specifications, Interface definitions, Behavioral simulations Library Manager Schematic Capture AHDL Verilog-A ADE Circuit Simulation

     Technology Selection:

     Process selection, Device Models, Layer definition, Layout rules, Primitives Library Manager Technology Files

     Component Level Design:

     Circuit topology, Device geometry, Component values, Symbol generation Library Manager Schematic Capture

     Circuit Analysis:

     Circuit Simulation, Design Corrections, Optimization, Verify Corners Library Manager Schematic Capture ADE Circuit Simulation

     System Integration:

     Schematic Hierarchy, Mixed-Level Simulations

     Physical Design:

     Layout, Layout Hierarchy

     Back End Verification:

     LVS, DRC, Parasitic Extraction, Parasitic Simulation Library Manager Diva or Assura Hierarchy Editor ADE Circuit Simulation

     Design Data Out

     Library Manager Hierarchy Editor ADE Verilog-A Circuit Simulation

     Library Manager Diva or Assura

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     Introduction to ADE 5.0

     1-27

     The Library Manager

     The Library Manager is a graphical data management tool.

     Object Sensitive Menus

     A library in the cds.lib file

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     Introduction to ADE 5.0

     1-29

     The Library Structure

     Library

     Training

     Cell

     VCO

     Symbol View

     Tools?ªLibrary Manager????

     Schematic View

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     Introduction to ADE 5.0

     1-31

     Creating a New Library

     In the CIW or the Library Manager, select File?ªNew?ªLibrary.

     s s s

     Specify the library name and path. Specify the design manager to use. For Physical Design and Verification, specify the ASCII technology file or technology file library to be attached to the new library. The new library is entered into the cds.lib file.

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     Introduction to ADE 5.0

     1-33

     Shared Technology Library

     This example shows several libraries sharing the same technology file library.

     Technology Library

     cellTechLib

     divaDRC.rul divaERC.rul

     techfile.cds

     symbolic devices divaEXT.rul divaLVS.rul master mux2

     Design Library

     Pcells

     Design Library

     ptransistor layout symbol

     ntransistor layout

     layout

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     Introduction to ADE 5.0

     1-35

     Technology File Stored in the Design Library

     This example shows a technology file being stored inside a design

library and not being shared with other libraries.

     Design Library master

     divaDRC.rul

     techfile.cds

     mux2

     divaERC.rul symbolic devices divaEXT.rul symbol layout

     divaLVS.rul

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     Introduction to ADE 5.0

     1-37

     Design Data Management

     s s s s

     Version control Configuration management Access control Release process

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     Introduction to ADE 5.0

     1-39

     Overview of Schematic Entry Flow

     Open Design

     Add Component Instances

     Add or Edit Component Parameters

     Add Pins

     Add and Name Wires

     Check Schematic

     Save

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     Introduction to ADE 5.0

     1-41

     Overview of Circuit Simulation

     Design Hierarchy or Test Circuit

     (schematic view)

     Stimulus:

     analogLib: vpulse - or stimulus file - or schematic

     Transistor Level Schematic

     (symbol view) Schematic of amplifier

     Load

     analogLib: cap res - or schematic

     Analog Design Environment User Inputs

     Setup simulator Modify Design Variables Choose Analyses Select Model Files Netlist and Run Simulation Plot Simulation Results View waveforms Evaluate expressions

     Circuit Simulator

     Spectre (used in this class), Spectre/Verilog, cdsSpice, etc.

     OUT: IN:

     IN: Netlist, temperature, etc. OUT:.psf,.log, etc.

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     Introduction to ADE 5.0

     1-43

     Types of Circuit Simulation Analyses

     Circuit Simulation Software Spectre

     Single Point

     Single Sweep

     Multiple Sweep

     dc dcop sensitivity mismatch

     ac transient dc sweep ac sweep

     noise

     parametric corners Monte Carlo optimization yield

     RF Analyses RF Spectral Analysis

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     Introduction to ADE 5.0

     1-45

     Summary

     In this module we discussed:

     s s s s s s s s s s s

     Course objectives Course outline Class schedule Getting Help, including CDSDoc Design Framework II environment Using forms Creating a library Creating cells and cell views Overview of schematic capture Overview of circuit simulation in the Analog Design Environment Types of simulation analyses

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     Introduction to ADE 5.0

     1-47

     Labs

     Lab 1-1 Getting Started Lab 1-2 Top-Down System Modeling

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     Module 2: Schematic Entry

     Topics in this module

     s s s s s s s s

     The schematic capture flow Creating a schematic view Contents of a schematic Adding component instances Adding pins Adding wires Editing object properties Using Accelerator keys (also known as bindkeys) and

    schematic window icons Checking the schematic for errors Symbol generation and editing Using a design hierarchy

     s s s

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     Schematic Entry

     2-3

     Schematic Entry Flow

     Open Design

     Add Component Instances

     Add or Edit Component Parameters

     Add Pins

     Add and Name Wires

     Check Schematic

     Save

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     Schematic Entry

     2-5

     Contents of a Schematic

     Wire Tap

     Component Instance

     Pin

     Wire Label

     Instance Label

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     Schematic Entry

     2-7

     Creating a New Cellview

     In the CIW or Library Manager, select File?ªNew?ªCellview.

     Default View Name subject to override. Select:

     Composer-Schematic

     s

     Specify the Library Name, Cell Name, View Name, and Tool to use. The path to the cds.lib file will appear in the form and is not editable. Modify the Tool field to create a layout, verilog, symbol, schematic, vhdl, or ahdl view.

     s

     For an ADE schematic, select Composer-Schematic from the Tool cyclic field

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     Schematic Entry

     2-9

     Adding Component Instances

     Select Add?ªInstance or press the i key to display the Add Instance form.

     s

     Attach multipliers to values. Enter 1k (not 1 k) so that k is not mistaken as a variable. Parameter units, such as ohms, are implicit.

     s

     Use these buttons while placing components to control orientation.

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     Schematic Entry

     2-11

     Updating Design Objects

     s

     Select Edit?ªProperties?ªObjects or bindkey q to start the form. The Next and Previous buttons highlight single objects in a selected set. Use Design?ªRenumber Instances to renumber instances in a design.

     s

     Design?ªRenumber Instances Edit?ªProperties?ªObjects

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     Schematic Entry

     2-13

     Adding Sources and Ground

     Sources, taps, and grounds are instances of cells. Sample source cells are in the analogLib library.

     s

     Choose from independent, dependent, and piece-wise linear (PWL) sources. Choose tap and ground cells, which are used to establish global nets. An instance of the cell gnd is required in the design for DC convergence.

     vcca vcc vcca + gnd gnda gnda gnda gnda gnd vcc

     s s

     vdc +

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     Schematic Entry

     2-15

     Pins

     Pins have a user-defined Name and a Direction (input, output, or input/Output). Pins are one of three types:

     s s

     Schematic pins provide ports to a schematic. Symbol pins provide

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