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introduction of hardware algorithm verification platform

By Justin Allen,2014-10-16 17:52
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introduction of hardware algorithm verification platform

    Hardware Algorithm Verification Platform

    Chuan Du

    July, 2013

    Abstraction

    This article discusses Hardware Algorithm Verification Platform and lists

    one demonstration to show its performance. This platform includes hardware

    algorithm verification flow, hardware algorithm design flow and software

    algorithm generation for analysis of hardware performance.

INTRODUCTION

    FPGA technology is used for ultri-low latency trading particularly for HFT field. The algorithm plays important role in the trend. How to transplant software financial algorithm to hardware algorithm is important step for many engineers who wants to make achievements in this field. This Hardware Algorithm Verification Platform can help them achieve their goal to verify their hardware algorithm on the FPGA platform and compare the result with software result to evaluate the performance. This platform includes C/C++ algorithm development, FPGA system development and FPGA system verification which include all the design flows for the software and hardware algorithm design.

    Algorithm developers do not need to understand the detail of this platform. They just follow the algorithm development flow and verify the system.

Platform System Description

    Software PlatformSoftware Platform

    SoftwareNios IITimerResultSoftwareFile WriteAlgorithm

    DDRUARTDataInterfaceTCP SocketTCP/IPFile ReadSendconnectionFPGA HardwareData processETHERNETHardware TCP SocketInterfaceRAMResultAlgorithmReceiveFile Write

System feature list

    ; Socket TCP/IP protocol

    ; uCOS II Multi-thread design

    ; Nios II INICHE TCP/IP protocol stack

    ; 32 bit RSIC NiosII MicroProcess

    ; Perl Command line operation

    ; TCL Modelsim command line verification

    ; Ethernet connection can be change to other connection such as PCIE with no change in

    other modules

    ; Hardware float algorithm design

    ; Software float algorithm design

FPGA Hardware structure description

    Here is the mainly system structure of FPGA hardware algorithm design platform:

    In this structure, NiosII is Altera? MicroProcess which can run software in the FPGA. All devices are connected by the system bus and controlled by NiosII MicroProcess. Algorithm trader can use connect to platform by serial port connector. (Additional Ethernet interfaces can be added to connect to traders computer). RJ-45 is usual Ethernet interface which is used to connect to communicate with broker, data feed or financial servers through Internet.

    Algorithm system is the part which we can design trading algorithm instructions. Algorithm traders can design their trading algorithm on the Matlab, generate FPGA programs and integrate them into FPGA system very easily. Of course, if traders are professional about FPGA programming, they can use FPGA develop flow to design the algorithm and optimize the system in according to real environment.

TRADING PLATFORM

    FLASHDDR2Serial port FLASHDDR2connecter