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Stratix IV GT Schematic Review Worksheet

By Lisa Adams,2014-06-18 15:00
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Stratix IV GT Schematic Review Worksheet

    Stratix? IV GT Device Schematic Review Worksheet

    This document is intended to help you review your schematic and compare the pin usage against the Stratix IV GT Device Family Pin Connection Guidelines (PDF) version 1.3 and other referenced literature for this device family. The technical content is divided into focus areas such as FPGA

    power supplies, transceiver power supplies and pin usage, configuration, FPGA I/O, and external memory interfaces.

    Within each focus area, there is a table that contains the voltage or pin name for all of the dedicated and dual purpose pins for the device family. In some cases, the device density and package combination may not include some of the pins shown in this worksheet, you should cross

    reference with the pin-out file for your specific device. Links to the device pin-out files are provided at the top of each section.

Before you begin using this worksheet to review your schematic and commit to board layout, Altera highly recommends:

1) Review the latest version of the Stratix IV GT Errata Sheet (PDF) and the Knowledge Database for Stratix IV Device Known Issues and Stratix

    IV Device Handbook Known Issues.

2) Compile your design in the Quartus? II software to completion.

For example, there are many I/O related placement restrictions and VCCIO requirements for the I/O standards used in the device. If you do not

    have a complete project, then at a minimum a top level project should be used with all I/O pins defined, placed, and apply all of the configurable options that you plan to use. All I/O related megafunctions should also be included in the minimal project, including, but not limited to, external memory interfaces, PLLs, altgx, altlvds, and altddio. The I/O Analysis tool in the Pin Planner can then be used on the minimal project to validate the pinout in Quartus II software to assure there are no conflicts with the device rules and guidelines.

When using the I/O Analysis tool you must ensure there are no errors with your pinout. Additionally, you should check all warning and critical

    warning messages to evaluate their impact on your design. You can right click your mouse over any warning or critical warning message and

    select “Help”. This will bring open a new Help window with further information on the cause of the warning, and the action that is required.

    Stratix IV GT Schematic Review Worksheet 1.3 Page 1 of 82 DS-01012-1.3

For example, the following warning is generated when a PLL is driven by a global network where the source is a valid dedicated clock input pin,

    but the pin is not one dedicated to the particular PLL:

Warning: PLL "" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by

    a non-dedicated input

     Info: Input port INCLK[0] of node "" is driven by clock~clkctrl which is OUTCLK output port of Clock Control Block

    type node clock~clkctrl

The help file provides the following:

    CAUSE: The specified PLL's input clock is not driven by a dedicated input pin. As a result, the input clock delay will not be fully compensated

    by the PLL. Additionally, jitter performance depends on the switching rate of other design elements. This can also occur if a global

    signal assignment is applied to the clock input pin, which forces the clock to use the non-dedicated global clock network.

    ACTION: If you want compensation of the specified input clock or better jitter performance, connect the input clock only to an input pin, or

    assign the input pin only to a dedicated input clock location for the PLL. If you do not want compensation of the specified input clock,

    then set the PLL to No Compensation mode.

When assigning the input pin to the proper dedicated clock pin location, refer to Clock Networks and PLLs in Stratix IV Devices (PDF) for the

    proper port mapping of dedicated clock input pins to PLLs.

    There are many reports available for use after a successful compilation or I/O analysis. For example, you can use the “All Package Pins” and “I/O Bank Usage” reports within the Compilation – Fitter Resource Section to see all of the I/O standards and I/O configurable options that are assigned to all of the pins in your design, as well as view the required VCCIO for each I/O bank. These reports must match your schematic pin

    connections.

    Stratix IV GT Schematic Review Worksheet 1.3 Page 2 of 82 DS-01012-1.3

The review table has the following heading:

Plane/Signal Schematic Name Connection Guidelines Comments / Issues

    The first column (Plane/Signal) lists the FPGA voltage or signal pin name. You should only edit this column to remove dedicated or dual purpose pin names that are not available for your device density and package option.

    The second column (Schematic Name) is for you to enter your schematic name(s) for the signal(s) or plane connected to the FPGA pin(s).

    The third column (Connection Guidelines) should be considered “read only” as this contains Altera’s recommended connection guidelines for the voltage plane or signal.

    The fourth column (Comments/Issues) is an area provided as a “notepad” for you to comment on any deviations from the connection guidelines, and to verify guidelines are met. In many cases there are notes that provide further information and detail that compliment the connection guidelines.

Here is an example of how the worksheet can be used:

Plane/Signal Schematic Name Connection Guidelines Comments / Issues

     d by

    provided by Altera> Altera> +0.95V Connected to +0.95V plane, no VCC isolation is necessary.

    Missing low and medium range

    decoupling, check PDN.

    See Notes (1-1) (1-2).

Stratix IV GT Schematic Review Worksheet 1.3 Page 3 of 82

    DS-01012-1.3

Legal Note:

    PLEASE REVIEW THE FOLLOWING TERMS AND CONDITIONS CAREFULLY BEFORE USING THIS SCHEMATIC REVIEW WORKSHEET (“WORKSHEET”) PROVIDED TO YOU. BY USING THIS WORKSHEET, YOU INDICATE YOUR ACCEPTANCE OF SUCH TERMS AND CONDITIONS, WHICH CONSTITUTE THE LICENSE AGREEMENT ("AGREEMENT") BETWEEN YOU AND ALTERA CORPORATION OR ITS APPLICABLE SUBSIDIARIES ("ALTERA").

1. Subject to the terms and conditions of this Agreement, Altera grants to you, for no additional fee, a non-exclusive and non-transferable right to

    use this Worksheet for the sole purpose of verifying the validity of the pin connections of an Altera programmable logic device-based design. You

    may not use this Worksheet for any other purpose. There are no implied licenses granted under this Agreement, and all rights, except for those

    granted under this Agreement, remain with Altera.

2. Altera does not guarantee or imply the reliability, or serviceability, of this Worksheet or other items provided as part of this Worksheet. This

    Worksheet is provided 'AS IS'. ALTERA DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. ALTERA HAS NO OBLIGATION TO PROVIDE YOU WITH ANY SUPPORT OR MAINTENANCE.

3. In no event shall the aggregate liability of Altera relating to this Agreement or the subject matter hereof under any legal theory (whether in tort,

    contract, or otherwise), exceed One Hundred US Dollars (US$100.00). In no event shall Altera be liable for any lost revenue, lost profits, or other

    consequential, indirect, or special damages caused by your use of this Worksheet even if advised of the possibility of such damages.

    4. This Agreement may be terminated by either party for any reason at any time upon 30-days’ prior written notice. This Agreement shall be governed by the laws of the State of California, without regard to conflict of law or choice of law principles. You agree to submit to the exclusive

    jurisdiction of the courts in the County of Santa Clara, State of California for the resolution of any dispute or claim arising out of or relating to this

    Agreement. The parties hereby agree that the party who is not the substantially prevailing party with respect to a dispute, claim, or controversy

    relating to this Agreement shall pay the costs actually incurred by the substantially prevailing party in relation to such dispute, claim, or controversy,

    including attorneys' fees. Failure to enforce any term or condition of this Agreement shall not be deemed a waiver of the right to later enforce such

    term or condition or any other term or condition of the Agreement.

    BY USING THIS WORKSHEET, YOU ACKNOWLEDGE THAT YOU HAVE READ THIS AGREEMENT, UNDERSTAND IT, AND AGREE TO BE BOUND BY ITS TERMS AND CONDITIONS. YOU AND ALTERA FURTHER AGREE THAT IT IS THE COMPLETE AND EXCLUSIVE STATEMENT OF THE AGREEMENT BETWEEN YOU AND ALTERA, WHICH SUPERSEDES ANY PROPOSAL OR PRIOR AGREEMENT, ORAL OR WRITTEN, AND ANY OTHER COMMUNICATIONS BETWEEN YOU AND ALTERA RELATING TO THE SUBJECT MATTER OF THIS AGREEMENT.

    Stratix IV GT Schematic Review Worksheet 1.3 Page 4 of 82 DS-01012-1.3

    

Index

Section I: Power

    Section II: Configuration

    Section III: Transceiver

    Section IV: I/O

     a: Clock Pins

     b: Dedicated and Dual Purpose Pins

     c: Dual Purpose Differential I/O pins Section V: External Memory Interface Pins

     a: DDR/2 Interface Pins

     b: DDR/2 Termination Guidelines

     c: DDR3 Interface Pins

     d: DDR3 Termination Guidelines

     e: QDRII/+ Interface pins

     f: QDRII/+ Termination Guidelines Section VI: Document Revision History

Stratix IV GT Schematic Review Worksheet 1.3 Page 5 of 82

    DS-01012-1.3

Section I: Power

Stratix IV Recommended Reference Literature/Tool List

Stratix IV Pin Out Files

Stratix IV GT Device Family Pin Connection Guidelines (PDF)

Stratix IV Early Power Estimator

    Stratix IV Early Power Estimator User Guide (PDF)

Power Delivery Network (PDN) Tool For Stratix IV Devices

    Device-Specific Power Delivery Network (PDN) Tool User Guide (PDF)

PowerPlay Power Analyzer Support Resources

Altera Board Design Resource Center (General board design guidelines, PDN design, isolation, tools, and more)

    AN 583: Designing Power Isolation Filters with Ferrite Beads for Altera FPGAs (PDF)

AN 597: Getting Started Flow for Board Designs (PDF)

Stratix IV GT Errata Sheet (PDF)

Index

    Stratix IV GT Schematic Review Worksheet 1.3 Page 6 of 82

    DS-01012-1.3

    Plane/Signal Schematic Name Connection Guidelines Comments / Issues VCC All VCC pins require a 0.95V supply. Use the Verify Guidelines have been met or list

    Stratix IV Early Power Estimator to determine required actions for compliance.

    the current requirements for VCC and other

    power supplies. These pins may be tied to the See Notes (1-1) (1-2).

    same 0.95V plane as VCCHIP. With a proper

    isolation filter VCCD_PLL may be sourced

    from the same regulator as VCC.

    To successfully power-up and exit POR on

    production devices (non-ES), fully power VCC

    before VCCAUX begins to ramp. See the

    Stratix IV GT Errata Sheet (PDF) for details.

    VCC pins must not share breakout vias, each

    VCC pin should have a separate dedicated

    via to the power plane.

    Decoupling for these pins depends on the

    design decoupling requirements of the

    specific board.

Index Top of Section

    Stratix IV GT Schematic Review Worksheet 1.3 Page 7 of 82

    DS-01012-1.3

    Plane/Signal Schematic Name Connection Guidelines Comments / Issues VCCAUX Connect these pins to an isolated 2.5V linear Verify Guidelines have been met or list

    power supply. With a proper isolation filter required actions for compliance.

    these pins may be sourced from the same

    linear regulator as VCCA_PLL. See Notes (1-1) (1-2).

    To successfully power-up and exit POR on

    production devices (non-ES), fully power VCC

    before VCCAUX begins to ramp. See the

    Stratix IV GT Errata Sheet (PDF) for details.

    Decoupling for these pins depends on the

    design decoupling requirements of the

    specific board.

Index Top of Section

    Stratix IV GT Schematic Review Worksheet 1.3 Page 8 of 82

    DS-01012-1.3

    Plane/Signal Schematic Name Connection Guidelines Comments / Issues VCCIO[1..8][A,C], Connect these pin to 1.2V, 1.5V, 1.8V, 2.5V or Verify Guidelines have been met or list VCCIO[2,3,4,5,7,8]B 3.0V supplies, depending on the I/O standard required actions for compliance.

     connected to the specified bank.

    (not all pins are See Notes (1-1) (1-2). available in each When these pins require 2.5V they may be

    device / package tied to the same regulator as VCC_CLKIN,

    combination) VCCPGM and VCCPD, but only if each of

    these supplies require 2.5V sources.

    VCC_CLKIN has a set voltage of 2.5V, so

    excluding VCC_CLKIN you may tie these pins

    to the same regulator as VCCPGM and/or

    VCCPD as long as they all require the same

    voltage.

    Decoupling for these pins depends on the

    design decoupling requirements of the

    specific board.

Index Top of Section

    Stratix IV GT Schematic Review Worksheet 1.3 Page 9 of 82

    DS-01012-1.3

    Plane/Signal Schematic Name Connection Guidelines Comments / Issues VCCPD[1..8][A,C], The VCCPD pins require 2.5V or 3.0V and Verify Guidelines have been met or list VCCPD[2,3,4,5,7,8]B must ramp-up from 0 V to 2.5V or 3.0V within required actions for compliance.

     100ms when PORSEL is low, or 4ms when

    (not all pins are PORSEL is high to ensure successful See Notes (1-1) (1-2). available in each configuration.

    device / package

    combination) VCCPD voltage connection depends on the

    VCCIO voltage of the bank.

    VCCPD for 3.0V VCCIO is 3.0V,

    VCCPD for 2.5V/1.8V/1.5V/1.2V VCCIO is

    2.5V.

    When these pins require 2.5V they may be

    tied to the same regulator as VCC_CLKIN,

    VCCPGM and VCCIO, but only if each of

    these supplies require 2.5V sources.

    VCC_CLKIN has a set voltage of 2.5V, so

    excluding VCC_CLKIN you may tie these pins

    to the same regulator as VCCPGM and/or

    VCCIO as long as they all require the same

    voltage.

    Decoupling for these pins depends on the

    design decoupling requirements of the

    specific board.

Index Top of Section

    Stratix IV GT Schematic Review Worksheet 1.3 Page 10 of 82

    DS-01012-1.3

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