Observations in Characterizing a Commercial
MNOS EEPROM for Space
E. E. King, R. C. Lacoe, G. Eng, and M. S. Leung
The Aerospace Corporation
2350 E. El Segundo Blvd.
(310) 336-7898, email@example.com
Abstract––Qualifying a commercial Non-Volatile The MNOS transistor is programmed to a „1‟ by applying
Memory (NVM) component for space poses several 15 V across the gate insulator: 5 V to the gate, and about challenges: detailed information about the process and –10 V to the body (well). Under this bias condition, design is not likely to be available; long-term reliability electrons are injected into the gate insulator from the data are uncertain or insufficient; little, if any, radiation channel, where some of them are trapped (stored) in the data exist; and the data retention requirement for a space electron traps that are inherently found in silicon nitride. application is longer than for most commercial To erase this „1‟ (program a „0‟), the –10 V bias is applied
applications, generally exceeding ten years. In this paper, to the gate and 5 V is applied to the well. Under this bias we describe our experiences in characterizing and condition, holes are injected into the gate insulator from qualifying a commercial 1-Mbit EEPROM, the Hitachi the silicon substrate where they neutralize the trapped HN58C1001. Since the unique attribute of a NVM is its electrons. The –10 V used for programming is generated ability to retain stored data over long periods of time with by an on-chip negative high-voltage generator circuit. The no power applied to the component, our work focused on erase/write time is about 10 ms, and is controlled by an determining the data retention lifetime and developing a on-chip timer. A sense amplifier measures the drain procedure to screen potential early data retention failures current with 0 V on the gate and discriminates between from the part population. This paper also describes the written and erased („1‟ and „0‟ states, respectively) several interesting behaviors of the part, which were states of the memory transistor.
discovered during the aging tests. GateGate TABLE OF CONTENTS NN28 nm Si28 nm Si3344 1. INTRODUCTION 2. EXPERIMENT 3. SCREEN DEVELOPMENT N+ SourceN+ Source N+ DrainN+ Drain 4. CONCLUSIONS 1.6nm SiO1.6nm SiO22P wellP well 5. REFERENCES 6. ACKNOWLEDGMENTS N substrateN substrate 1. INTRODUCTION Figure 1. Schematic illustration of the MNOS memory The HN58C1001 is a 128k by 8 bit electrically erasable transistor used in the HN58C1001. and programmable read-only memory. The part is fabricated using a CMOS process with the addition of a The MNOS memory exhibits a high degree of non-Metal-Nitride-Oxide-Silicon (MNOS) transistor that is volatility due to its ability to retain the charge trapped in used as the data storage element . The MNOS the gate insulator even when the power to the device is transistor is schematically illustrated in Figure 1. A data turned off. The memory transistor is not totally bit is stored in the MNOS transistor in the form of charge nonvolatile, however, because the trapped charge that is trapped in the silicon nitride film above the channel. (whether holes or electrons) does slowly leak out of the The presence or absence of charge results in a change in nitride layer over time, resulting in a narrowing of the threshold voltage between two states that are defined as a threshold voltage window that defines the „1‟ and „0‟ „1‟ and „0.‟ The transistor is interrogated by detecting the states. The dominant charge decay mechanism for the channel current that flows when the gate voltage is set at MNOS transistor has been found to be thermally activated 0 V. emission of the charge out of the traps . However, another concern in space is that the electron-hole pairs