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Review

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ReviewReview

    Review

Review,andPerspectiveofArchitectureDevelopment

    ;forDynamicRandomAccessMemory

    ;WANGYuxing.WUJin.

    ;(1.WuxiProfessionalCollegeofScienceandTechnology,WuXi214028,CHN; ;2.SoutheastUniversity,WuXi214135,CHN)

    ;Abstract:Discussedisareviewandperspectiveofarchitecture,materialsandprocesstechnologyfor

    ;dynamicrandomaccessmemory(DRAM)applications.Keychallengesofthetransistorandcapacitorscaling

    ;fromDRAMwillbereviewed.Tocontinuescalingdown,multi-gatedeviceswithverythinsiliconchannelsare

    ;mostpromising.Severa1architectureslikeFinffieldeffecttransistor(Fin-FET),Waferbondeddoublegateand

    ;silicononnothing(SON)gate-all-aroundhavebeendemonstratedwithgoodelectricalcharacteristics.An

    ;overviewoftheevolutionofCapacitortechnologyisalsopresentedfromtheearlydaysofplanarpoly/insulator/

    ;silicon(PIS)caDacitorstothemeta1/insulator/metal(MIM)capacitorsusedfortoday5Onmtechnologynode

    ;andbelow.IncomparingTa2Os,HfO2andA12OaaShigh

    dielectricforuseinDRAMtechnology,A12Oais

    ;foundtogiveagoodcompromisebetweencapacitorperformanceandmanufacturabmtyusedinMIM

    ;architecture.

    ;Keywords:DRAM;multi-gate;Fin-FET;high-kdielectric;capacitor ;CLCnumber:TN304Documentcode:AArticleID:10070206(2008)03018606

    ;1Introduction

    ;Dynamicrandomaccessmemory(DRAM)

    ;technologyhasprogressedatarapidpacesincethe

    ;inventionoftheonetransistor/onecapacitorcellin

    ;thelate1960s[,asshowninFig.1.Eversince

    ;then,retentiontimeandpowerconsumption

    ;constraintscharacterizespecialboundaryconditions

    ;forDRAMdevicedesign.DRAMtechnologyis

    ;optimizedforlowcostandhighyieldwitha

    ;particularfocusonlowleakagedevices.

    ;2MetalOxideSemiconductor(MoS)

    ;Scale

    ;2

;l52O253O3540

    ;DRAM(:elicapaeitance/fF

    ;Fig.1Definitionofaleakagecurrentdensityconsidering

    ;refreshpropertyonDRAM,Retentiontime

    ;dependsonleakagecurrent

    ;Inthepast30yearswiththesuccessofscaling,

    ;eachtechnologygenerationbecamesmalleraccordingtoMoore’slaw.However,therearestillthree

    ;mainlimitationsforperformanceincrease,asindicatedinFig.2.GateleakagestopsSi02scaling;and

    ;sourcedrainleakagereductionneedshigherchanneldopingandshallowerjunctions.Thisincreases

    ;junctioncapacitance,junctionleakage,gateinduceddraincurrents,reducescarriermobilityand

    ;Reeeiveddate:20080526;reviseddate:20080721

    ;?

    ;186?

    ;_}?吧媳r1

    ;

    ;Vol,14No.3WANGYX,eta1.ReviewandPerspectiveofArchitectureDevelopmentforDynamicRandomAccessMemory

    ;lncreasesparasiticreslstance.

    ;RegardingDRAM,severalconstraintscanalsobe

    ;foreseen.Thestoragecapacitanceatsmallcellsize

    ;andalowleakagecelltransistorbecomeacritical

    ;issue.Nowthecor~ventionalplanartransistoris

    ;usedinDRAMasshowninFig.2,therefore,new

    ;deviceandmemorycellconceptswillbeneededto

    ;sustainthedemandsforthefuturegenerations.On

    ;Fig.2Devicescalinglimitsofbulkdevice:sourcedrain,

    ;gateandjunctionleakagecurrents

    ;thewaytobetterdevices,internationaltechnologyroadmapforsemiconductorsfITRS)proposestwo

    ;strategies.Thefirstistoimplementnewmaterialsasperformanceboosters,includinghighkdie1ectrics

    ;andmetalgates,highmobilitychannelsandlowresistanceormetalsourcedrainjunctions.Thiswill

    ;improvetheperformanceofbulktransistorsremarkably.Thesecondistodevelopnewdevicestructures

    ;withbetterelectrostaticcontrol,likefullydepletedSOIandmultigatedevices.Theycana

    1sobeutilized

    ;inDRAMaslowleakagecelltransistor.

    ;2.1UltraThinSOI

    ;Mostproblemsduetoshortchanneleffectsarerelatedtothesiliconbulk.Silicononinsulator

uses

    ;onlyathinsiliconlayerforthechannel,whichisisolatedfromthebulkbyaburiedoxide.Seve

    ra1

    ;semiconductorcompanieshavealreadyswitchedtosilicononinsulator(SOI),especia11vf

    orhigh

    ;performancemicroProcessors.Typically,thethicknessofSilayerisintherangeof5Onm

    100nmand

    ;thedopingconcentrationsarecomparabletobulkdevices.Butfurtherdown-scalingfacessi

    milarissues

    ;asbulk.

    ;2.2MultigateDevices

    ;Furtherreductionofthegatelengthwillrequire ;twoorroofegatestocontrolthechanneltogether. ;Theadvantageofmultigateistosuppressthedrain

    ;fieldmuchmoreeffectively.

    ;ThisisshowninFig.3

    ;byusingthesamesimulationconditionsasshownin ;Fig.4,butaddingabottomgatetothe3OnmSOI ;transistor.AsshowninFig.3,theelectrostatic ;potentialbarrierismuchhigherthanthatinthe ;singlegatedevice.Thebetterelectrostaticcontro1 ;resultsinasteepersubthresholdslope.Themain

    ;challengeformultigatedevicesistofindaproper

    ;architectureandprocessflowcomparableinvield ;andcoststobulkcomplementarymetaloxide ;semiconductor(CMOS).Threepromisingconcepts ;havebeeninvestigated.AsshowninFig.5,the ;firstisaplanardoublegateSOItransistor[.the

    ;secondisagate-allarounddevicebasedonSONE4]

    ;andthethirdisFinFETtype[.Akevissuefor

    ;multigatetransistorsistodevelopamanufacture ;ableprocesswithself-alignedgatestosourcedrain ;10

    ;30nm

    ;PotentiaW

    ;

    ;Fig.3Electrostaticpotentialindoublegatetransistor ;with30nmgatelengthand10nmSithickness ;(g0V,Va1.1Vmid-gapgatemateria1)

    ;Fig.4Potentialdistributionin30nmsinglegateSOI ;transistor(Vg0V,Vd1.1Vmidgapgate

    ;materia1)

    ;Fig.5Threearchitecturesformultigatedevice:plannar

    ;doublegate;gateallaroundSONandFin-FET

;?

    ;187?

    ;

    ;SemiconductorPhotonicsandTechnologyAug.2008 ;regions?

    ;2.2.1WaferBondedPlanarDoubleGate

    ;TheplanardoublegatetransistorLJisan ;evolutionoftheultrathinSOItransistor.Atopand ;abottomgateareusedforabettercontrolofthe ;channe1.Processingstartswiththebottomgate ;usingaSO1waferwithathinsiliconlayer,shown ;inFig.6.Afterlithogrphyandetching,thegateis ;encapsulatedwithdielectriclayersandplanarized ;withchem.icalmechanicalpolish(CMP).Next,a ;handlewaferwithanoxidelayerisbondedontothe ;waferisremovedcompletelyandthenistheburied ;thinSilayerandthetopgate,sourcedrainregions ;transistor.Theadvantagesfordoublegate(DG) ;csilicon

    ;Polysilicon

    ;Siliconoxide

    ;SiliconNitride

    ;Fig.6Processflowforawaferbondedplanardoublegate ;waferwiththebottomgate.ThenthebulkSiofthe ;oxide.Nowagatedielectricoxideisgrownonthe ;andcontactsareprocessedlikeinasinglegateSOI ;meta1oxidesemiconductorfieldeffecttransistors ;(MOSFETs)include:idea1subthresholdslope;volumeinversion(forsymmetricDG);s

    ettingof

    ;thresholdvoltagebythegateworkfunctionthusavoidingdopantsandassociatednumberfl

    uctuation

    ;effects.etc.Thedouble-gateMOSFETarchitectureisapotentialsolutiontoovercomeshort

    channel

    ;effectsinthe65nmITRSnode.

    ;2.2.2SilicononNothingGateAllAround

    ;Thesecondapproachformultigatearchitectures

    ;isbasedonsilicon~,whichusesbulkSiwafers ;insteadofSOI.ASiGelayerisgrownwithselective ;chemicalvapordeposition(CVD)epitaxyandontop ;non-selectivelyathinSilayerisforthechannel, ;showninFig.7.NextSiGelayerisremovedbyan ;isotropicetchprocess.Thenthegatedielectricis ;depositedaroundthesiliconbridgefollowedbythe ;gatematerialofpolySioraTiNmetalgate.GateFig.7Gateallaroundtransistorprocessingb

asedon

    ;SONwithSiGelayer

    ;length(40nm)andverythinSichannelsdownto15 ;nmhavebeensuccessfullyfabricated;一引.

    ;Thisdeviceis

    ;switchingdeviceinarrayedstructuressuchashighdensity

    accessmemory(SRAM)cellswhereasmall ;staticrandom

    ;essentia1.

    ;2.2.3Finl-FET

    ;TheFinFETcanrealizeadoubleortrigate

    ;structurewithrelativelysimpleprocessingas ;showednFig.8.AsDRAMcellsizeshrinksto

    ;sub100nm,itbecomescriticallyimportantto ;realizesufficienton-currentofthearraytransistor ;becauseofthelimitedchannelwidthandthe

    ;degradedelectronmobilityduetoincreasedchannel ;doping.Moreover,theconventionalMOSFET

    ;scalingtechniquesshouldnotbeappliedtothearray ;?188?

    ;particularlybeneficialwhenitisusedasa

    ;dynamicrandom-accessmemory(DRAM)and

    ;devicegeometryandlowleakagecurrentare

    ;Fig.8Bird’seyeviewofdouble/tripleMOSFET

    ;transistor,becausethegateoxidethicknessshould ;

    ;Vo1.14No.3WANGYX,eta1.ReviewandPerspectiveofArchitectureDevelopmentforD

    ynamicRandomAccessMemory

    ;notbeshrunkinviewoftherequirementofextremelowoff-currentforthedataretention,whi

    ch

    ;restrictsthethresholdvoltagetoaround1Vwithoutextrachanneldoping.Inviewofthese

    ;considerations,adifferentstructuralapproachforarrayfieldeffecttransistor(FET)ofDRA

    Mis

    ;indispensable.Also,anewapproachisrequiredwhichincreasesstoragecapacitancewithin

    alimited

    ;capacitorarea.

    ;InordertoovercomethearrayFETconstraints, ;trenchisolatedtransistorusingsidewallgates(TIS) ;orFinarray-FgTapproachcanbeadoptedto

    ;improvethetransistorperformanceasincaseofSOI ;transistors.Fig.9showsabird’SeyeviewofTIS-

    ;ArrayFET.TISgatestructure,whichconsistsof ;topgateandsidewallgateenableshighon-current

    ;and1OWoff-currentsimultaneouslybecauseoftheFig. ;9TIS/FinarrayFETDRAM

    ;doublegatestructureandhighgatecontro11abIlity.ThethinnerTfinisexpectedtoresultinadramatic

    ;reductionofoff-current,whichisverysuitableforarraytransistors.TIShasgreatadvantage

    s,namely,

    ;highdrivabilityandcompactareawhicharesuitableforDRAMarraydevice.

    ;3CapacityScale

    ;3.1CapacityArchitectureEvolution

    ;DRAMcel1consistsofanaccesstransistoranda ;storagecapacitor(1T/1C).Therearetwotypesof ;storagecapacitors,stackedcapacitorsandtrench

    ;capacitors,ofwhichthe1atteroffershighest ;density,attheexpenseofprocesscomplexity. ;Trenchcapacitorsarelesssuitableforintegrationof ;highkdielectricsbecausetheyareformedbeforethe ;transistors,andtheyneedhightemperature ;anneals.Technica1innovationincapacitor ;processingcontinuedoverthepast20yearsinthe ;industry,enablingDRAMscalingintothesub

    ;100nmregimeoftoday.Fig.10illustratesthe ;successivearchitecturesadopted.Inthefollowing ;summaryofDRAMcapacitortechnologysince ;1982,nodistinctionismadebetweenstandard ;DRAMasthebothtypesaredrivenbysimilar ;concernslikehighcapacitance,highbreakdown ;voltageandhighcapacitordensity.

    ;Between1982

    ;and1985,DRAMdensityincreasedfrom64KBto1 ;MBusingplanar2Dcapacitors.{r0mtheearly

    ;PISstructure(poly-insulatorsilicon:Fig.10a)with

    ;gateoxidedielectrictoPIPcapacitors(poly- ;insulator-poly:Fig.10b)whichallowadjustmentof ;bll

    ;con

    ;Fig.10DRAMarchitectureevolution

    ;Fig.11HSGbottomelectrodein120nmDRAM

    ;dielectricthicknessandcapacitance.Thestacked ;?

    ;l89?

    ;

    ;SemiconductorPhotonicsandTechnologyAug.2008 ;capacitor,firstproposedin1978byKoyanagieta1.[.],wasappliedforindustrial1Mbintegr