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K4S643232C-TC60

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K4S643232C CMOS SDRAM 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL www.Chinadz.Com Revision 1.1 November 1999 Samsung Electronics reserves the right to change products or specification without notice. - 1 - REV. 1.1 Nov. '99 Free Datasheet Download http://www.Chinadz.Com http://www.Icver.Com ..

    K4S643232C CMOS SDRAM

    2M x 32 SDRAM

    512K x 32bit x 4 Banks

    Synchronous DRAM

    LVTTL

    www.Chinadz.Com

    Revision 1.1

    November 1999

    Samsung Electronics reserves the right to change products or specification without notice.

    REV. 1.1 Nov. '99 - 1 -

    Free Datasheet Download http://www.Chinadz.Com http://www.Icver.Com

    K4S643232C CMOS SDRAM

Revision History

Revision 1.1 (November 17th, 1999)

     Corrected typo in ordering information on page 3

Revision 1.0 (October, 1999)

     Changed part number from KM432S2030CT-G/F to K4S643232C-TC/TL according to re-organized code system

    www.Chinadz.Com

    REV. 1.1 Nov. '99 - 2 -

    Free Datasheet Download http://www.Chinadz.Com http://www.Icver.Com

    K4S643232C CMOS SDRAM

512K x 32Bit x 4 Banks Synchronous DRAM

    FEATURES GENERAL DESCRIPTION

     3.3V power supply The K4S643232C is 67,108,864 bits synchronous high data LVTTL compatible with multiplexed address rate Dynamic RAM organized as 4 x 524,288 words by 32 bits, Four banks operation fabricated with SAMSUNGs high performance CMOS technol- MRS cycle with address key programs ogy. Synchronous design allows precise cycle control with

    -. CAS latency (2 & 3) the

    -. Burst length (1, 2, 4, 8 & Full page) use of system clock. I/O transactions are possible on -. Burst type (Sequential & Interleave) every All inputs are sampled at the positive going edge of the system clock cycle. Range of operating frequencies, programmable clock burst length and programmable latencies allow the same device Burst read single-bit write operation to be useful for a variety of high bandwidth, high DQM for masking performance Auto & self refresh Part NO. Max Freq. Interface Package memory system applications. 15.6us refresh duty cycle K4S643232C-TC/L55 183MHz K4S643232C-TC/L60 166MHz ORDERING INFORMATION 86 K4S643232C-TC/L70 143MHz LVTTL TSOP(II) K4S643232C-TC/L80 125MHz

    K4S643232C-TC/L10 100MHz

    FUNCTIONAL BLOCK DIAGRAM

    I / O C o n t r o l O u t p u t B u f f e r LWE

    Data Input Register

    LDQM

    Bank Select S e n s e A M P

    512K x 32 512K x 32 DQi 512K x 32 CLK 512K x 32

    ADD www.Chinadz.Com

    Column Decoder

    Latency & Burst Length

    LCKE Programming Register R o w D e c o d e r C o l . B u f f e r LRAS LCBR LWE LDQM LWCBR LCAS

    Timing Register

    L C B R R o w B u f f e r

    CLK CKE CS RAS CAS WE DQM R e f r e s h C o u n t e r L R A S * Samsung Electronics reserves the right to change products or specification without

    notice.

    A d d r e s s R e g i s t e r REV. 1.1 Nov. '99 - 3 -

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    K4S643232C CMOS SDRAM

PIN CONFIGURATION (Top view)

    VDD SS 1 V86 DQ0 DQ15 2 85 VDDQ VSSQ 3 84 DQ1 DQ14 4 83 DQ2 DQ13 5 82 VSSQ VDDQ 6 81 DQ3 DQ12 7 80 DQ4 DQ11 8 79 VDDQ VSSQ 9 78 DQ5 DQ10 10 77 DQ6 DQ9 11 76 VSSQ VDDQ 12 75 DQ7 DQ8 13 74 N.C N.C 14 73 VDD VSS 15 72 DQM0 DQM1 16 71 WE N.C 17 70 CAS N.C 18 69 RAS CLK 19 68 CS CKE 20 67 N.C A9 21 66 BA0 A8 22 65 BA1 A7 23 64 A10/AP A6 24 63 A0 A5 25 62 A1 A4 26 61 A2 A3 27 60 DQM2 DQM3 28 59 VDD VSS 29 58 N.C N.C 30 57 DQ16 DQ31 31 56 VSSQ VDDQ 32 55 DQ17 DQ30 33 54 DQ18 DQ29 34 53 VDDQ 35 VSSQ 52

    DQ19 36 DQ28 51 www.Chinadz.Com DQ20 37 DQ27 50 VSSQ DDQ 38 V49 DQ21 DQ26 39 48 DQ22 DQ25 40 47 VDDQ VSSQ 41 46 DQ23 DQ24 42 45 86Pin TSOP (II) VDD 43 VSS 44 (400mil x 875mil)

    (0.5 mm Pin pitch)

    REV. 1.1 Nov. '99 - 4 -

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    K4S643232C CMOS SDRAM

PIN FUNCTION DESCRIPTION

    Pin Name Input Function

    CLK System clock Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CS Chip select CLK, CKE and DQM. Masks system clock to freeze operation from the next clock cycle. CKE Clock enable CKE should be enabled at least one cycle prior to new command.

    Disables input buffers for power down mode. Row/column addresses are multiplexed on the same pins. A ~ Address 0Row address : RA0 ~ RA10, Column address : CA0 ~ CA7 A10 Selects bank to be activated during row address latch time. BA0,1 Bank select address Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. RAS Row address strobe Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. CAS Column address strobe Enables column access. Enables write operation and row precharge. WE Write enable Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. DQM0 ~ 3 Data input/output mask Blocks data input when DQM active. DQ0 ~ 31 Data input/output Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. VDD/VSS Power supply/ground Isolated power supply and ground for the output buffers to provide improved noise VDDQ/VSSQ Data output power/ground immunity. NC No Connection This pin is recommended to be left No connection on the device. ABSOLUTE MAXIMUM RATINGS

     Symbol Value Unit Parameter VIN, VOUT -1.0 ~ 4.6 V Voltage on any pin relative to Vss VDD, VDDQ -1.0 ~ 4.6 V Voltage on VDD supply relative to Vss TSTG -55 ~ +150 C Storage temperature PD 1 W Power dissipation www.Chinadz.Com mA IOS 50 Short circuit current

    Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.

    Functional operation should be restricted to recommended operating condition.

    Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

    CAPACITANCE (V = 3.3V, T = 23C, f = 1MHz, V REF = 1.4V;! 200 mV) DD A

    Pin Unit Symbol Min Max Clock CCLK 2.5 4 pF RAS, CAS, WE, CS, CKE, DQM CIN 2.5 4.5 pF Address CADD 2.5 4.5 pF DQ0 ~ DQ31 COUT 4.0 6.5 pF

    REV. 1.1 Nov. '99 - 5 -

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    K4S643232C CMOS SDRAM

DC OPERATING CONDITIONS

    Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70C)

    Parameter Max Symbol Min Typ Unit Note Supply voltage VDD, VDDQ 3.0 3.3 3.6 V 4 Input logic high voltage VIH 2.0 3.0 VDDQ+0.3 V 1 Input logic low voltage VIL -0.3 0 0.8 V 2 Output logic high voltage VOH 2.4 - - V IOH = -2mA Output logic low voltage VOL - - 0.4 V IOL = 2mA Input leakage current ILI -10 - 10 uA 3 Notes : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is; 3ns.

    2. VIL (min) = -2.0V AC. The undershoot voltage duration is; 3ns.

    3. Any input 0V; VIN; VDDQ,

    Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

    4. The VDD condition of K4S643232C-55/60 is 3.135V~3.6V.

    DC CHARACTERISTICS

    (Recommended operating condition unless otherwise noted, TA = 0 to 70C)

    Version CAS Parameter Symbol Test Condition Unit Note Latency -55 -60 -80 -10 -70 Burst length = 1 3 140 140 130 130 115 Operating current tRC; tRC(min) CC1 ImA 2 (One bank active) 2 - - - 130 115 Io = 0 mA 2 ICC2P CKE; VIL(max), tCC = 15ns Precharge standby current mA in power-down mode ICC2PS CKE & CLK; VIL(max), tCC =;; 2 IH(min), CS; VIH(min), tCC = 15ns CKE; VICC2N 20 mA Input signals are changed one time during 30ns Precharge standby current in non power-down mode CKE; VIH(min), CLK; VIL(max), tCC =;; ICC2NS 10 mA Input signals are stable CKE; VIL(max), tCC = 15ns ICC3P 3 Active standby current in mA power-down mode ICC3PS CKE & CLK; VIL(max), tCC =;; 3 CKE; VIH(min), CS; VIH(min), tCC = 15ns ICC3N 30 mA Active standby current in www.Chinadz.Com Input signals are changed one time during 30ns non power-down mode CKE; VIH(min), CLK; VIL(max), tCC =;; (One bank active) CC3NS 20 mA IInput signals are stable Io = 0 mA 180 3 220 200 150 130 Operating current Page burst CC4 ImA 2 (Burst mode) 2 Banks activated - 2 - - 130 110 3 200 200 180 160 150 tRC; tRC(min) Refresh current ICC5 3 mA - 2 - - 160 150 mA 4 2 CKE; 0.2V Self refresh current ICC6 450 uA 5 Notes : 1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL.

    2. Measured with outputs open.

    3. Refresh period is 64ms.

    4. K4S643232C-TC**

    5. K4S643232C-TL**

    REV. 1.1 Nov. '99 - 6 -

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    K4S643232C CMOS SDRAM

AC OPERATING TEST CONDITIONS (V = 3.3V;! 0.3V, T = 0 to 70C) DD A

    Parameter Unit Value AC input levels (Vih/Vil) 2.4/0.4 V Input timing measurement reference level 1.4 V Input rise and fall time tr/tf = 1/1 ns Output timing measurement reference level 1.4 V Output load condition See Fig. 2

    3.3V Vtt = 1.4V

    1200; 50;

    VOH (DC) = 2.4V, IOH = -2mA Z0 = 50; Output Output VOL (DC) = 0.4V, IOL = 2mA

    *1 *1 50pF50pF 870;

    (Fig. 1) DC output load circuit (Fig. 2) AC output load circuit

Note : 1. The DC/AC Test Output Load of K4S643232C-55/60/70 is 30pF.

    2. The VDD condition of K4S643232C-55/60 is 3.135V~3.6V.

    OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

    Version Parameter Symbol Note Unit -70 -55 -60 -80 -10 3 2 CAS Latency CL CLK 2 3 2 3 2 3 3 2 CLK cycle time tCC(min) ns 5.5 10 - 6 - 7 - 8 10 12 Row active to row active delay tRRD(min) CLK 2 1 RAS to CAS delay tRCD(min) CLK 1 3 - 3 - 3 - 3 2 2 2 Row precharge time tRP(min) CLK 1 3 - 3 - 3 - 3 2 2 2 www.Chinadz.Com tRAS(min) CLK 1 7 - 7 - 7 - 6 5 5 4 Row active time us 100 RAS(max) t

    10 CLK Row cycle time tRC(min) 10 - 10 - - 9 7 7 6 1 10 CLK tRFC(min) 12 - 12 - - 9 7 7 6 1,6 Row cycle time in Auto refresh

    CLK Last data in to row precharge tRDL(min) 2 2, 5

    CLK Last data in to new col.address delay tCDL(min) 1 2

    CLK Last data in to burst stop tBDL(min) 1 2

    CLK Col. address to col. address delay tCCD(min) 1

    2 CLK Mode Register Set cycle time tMRS(min)

     2 CAS Latency=3 ea Number of valid output data 4 1 CAS Latency=2

    Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then

    rounding off to the next higher integer. Refer to the following ns-unit based AC table.

    REV. 1.1 Nov. '99 - 7 -

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K4S643232C CMOS SDRAM

     Version Symbol Unit Parameter -70 -55 -60 -80 -10 7 5.5 6 8 10 tCC(min) ns CLK cycle time

    14 tRRD(min) ns 11 12 16 20 Row active to row active delay

    tRCD(min) ns 16.5 18 21 20 20 RAS to CAS delay

    tRP(min) ns 16.5 18 21 20 20 Row precharge time

     tRAS(min) ns 38.5 42 49 48 48 Row active time tRAS(max) us 100 tRC(min) ns 70 55 60 70 70 Row cycle time

    70 tRFC(min) ns 66 72 70 70 Row cycle time in Auto refresh

    2. Minimum delay is required to complete write.

    3. All parts allow every cycle column address change.

    4. In case of row precharge interrupt, auto precharge and read burst stop.

    5. For -55/60/70/80/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket

    code "NV". From the next generation, tRDL will be only 2CLK for every clock frequency.

    6. A new command should be issued after self refersh exit followed by tRFC. AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

    -55 -60 -70 -80 -10 Parameter Symbol Unit Note Max Min Min Max Min Max Min Max Min Max CAS Latency=3 10 5.5 6 7 8 1000 1000 1000 CC CLK cycle time t1000 ns 1 1000 - - - 10 CAS Latency=2 12 6 5 5.5 5.5 6 CAS Latency=3 - - - - - CLK to valid tSAC ns 1, 2 output delay - - - - CAS Latency=2 - - - 6 - 8 Output data OH 2 - 2.5 - 2.5 - 2.5 - 2.5 - tns 2 2 2.5 CAS Latency=3 - CLK high pulse width tCH ns 3 3.5 3 3 - - - - - - - CAS Latency=2 2.5 2 CAS Latency=3 - tCL - 3 - 3 - 3.5 - ns 3 CLK low pulse width - - - CAS Latency=2 www.Chinadz.Com 1.5 CAS Latency=3 1.5 1.75 - Input setup time SS - - 2 - 2.5 - ns 3 t - CAS Latency=2 - - - 1 Input hold time SH - t- 1 - 1 - ns 3 1 - 1 1 1 CLK to output in Low-Z tSLZ 1 - - - 1 - 1 - ns 2 - CAS Latency=3 - 5 5.5 - 5.5 - 6 - 6 CLK to output tSHZ ns in Hi-Z - - - - - - 6 - 8 - CAS Latency=2

    Note : 1. Parameters depend on programmed CAS latency.

    2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

    3. Assumed input rise and fall time (tr & tf)=1ns.

    If tr & tf is longer than 1ns, transient time compensation should be considered,

    i.e., [(tr + tf)/2-1]ns should be added to the parameter.

    REV. 1.1 Nov. '99 - 8 -

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    K4S643232C CMOS SDRAM

SIMPLIFIED TRUTH TABLE

     , CKEn-1 CKEn 0,1 A10/AP Note CS RAS CAS WE DQM BACommand A ~ A0 9

    H X L L L L X OP code 1,2 Register Mode register set H 3 Auto refresh H L L L H X X L 3 Entry Refresh Self 3 L H H H refresh H Exit L X X 3 H X X X Bank active & row addr. X H X V Row address L L H H Column Read & Auto precharge disable L 4 address H X X V L H L H column address (A ~ A 0 Auto precharge enable H 4,5 ) 7 Write & Auto precharge disable L 4 Column H X L H L L X V column address address Auto precharge enable H 4,5 (A ~ A 0 ) 7Burst Stop 6 H X L H H L X X

     Bank selection V L Precharge H X L L H L X X All banks X H

    H X X X Entry H L X Clock suspend or X L V V V active power down Exit L H X X X X X H X X X Entry H L X L H H H Precharge power down mode X H X X X Exit L H X L V V V X DQM H V X 7 X X X H No operation command H X X X H L H H

    (V=Valid, X=Dont care, H=Logic high, L=Logic low) Notes :1. OP Code : Operand code

    A ~ A10 & BA0 ~ BA1 : Program keys. (@ MRS) 02. MRS can be issued only at all banks precharge state. www.Chinadz.Com A new command can be issued after 2 CLK cycles of MRS.

    3. Auto refresh functions are as same as CBR refresh of DRAM.

    The automatical precharge without row precharge command is meant by "Auto".

    Auto/self refresh can be issued only at all banks precharge state.

    4. BA0 ~ BA1 : Bank select addresses.

    If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.

    If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.

    If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.

    If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.

    If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.

    5. During burst read or write with auto precharge, new read/write command can not be issued.

    Another bank read/write command can be issued after the end of burst.

    New row active of the associated bank can be issued at tRP after the end of burst.

    6. Burst stop command is valid at every burst length.

    7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),

    but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

    REV. 1.1 Nov. '99 - 9 -

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    K4S643232C CMOS SDRAM

MODE REGISTER FIELD TABLE TO PROGRAM MODES

Register Programmed with MRS

    Address BA0 ~ BA1 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Function RFU RFU W.B.L CAS Latency BT Burst Length TM

    Test Mode CAS Latency Burst Type Burst Length

    Type A A7 6 A5 A4 Latency A3 Type A2 A1 A0 BT = 0 BT = 1 A8 0 Mode Register Set 0 0 0 Reserved Sequential 1 1 0 0 0 0 0

    1 0 0 1 Reserved Reserved Interleave 2 2 1 0 0 1 0

    0 1 0 0 Reserved 2 4 4 0 1 0 1

    0 1 1 8 1 Reserved 3 0 1 1 8 1

    1 0 0 Reserved 1 0 0 Reserved Reserved Write Burst Length

    1 0 1 Reserved Reserved Reserved 1 0 1 Length A 9 1 1 0 Reserved 1 1 0 Reserved Reserved Burst 0 1 1 1 Reserved Full Page Reserved 1 1 1 Single Bit 1

    Full Page Length : x32 (256) POWER UP SEQUENCE

SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

    1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs. 2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.

    3. Issue precharge commands for all banks of the devices.

    4. Issue 2 or more auto-refresh commands.

    5. Issue a mode register set command to initialize the mode register.

    cf.) Sequence of 4 & 5 is regardless of the order.

The device is now ready for normal operation.

Note : 1. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.

    2. RFU (Reserved for future use) should stay "0" during MRS cycle.

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    REV. 1.1 Nov. '99 - 10

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