Filename=”AET_ch3.doc”
VHDL & VHDL-AMS Object Classes and Data Types
In VHDL, a data object holds a value of some specified type and can be classified into one of the following six classes: constants, variables, signals, file, quantity, terminal. The declaration syntax is:
OBJECT_CLASS identifier [,identifier ...] :TYPE [:=value];
1.1 Constant Class
An object of class constant holds a single value of of a given type. It must be assigned a value upon declaration, and the value can‟t be changed subsequently. The declaration syntax is:
CONSTANT identifier [,identifier ...]:TYPE:=value;
Example:
CONSTANT a1:REAL :=1.2;
CONSTANT word_size:INTEGER:= 16;
1.2 Variable Class
An object of class variable holds a single value of a given type. It can be assigned new value any number of times during program executions. It needs not be initialized upon declaration. The declaration syntax is:
VARIABLE identifier [,identifier ...]:TYPE [:=value];
Example:
VARIABLE counter: BIT_VECTOR(3 DOWNTO 0) := “0000”;
VARIABLE sum: REAL;
Variables are changed by executing an assignment operator. For example,
counter := “0001”;
sum := 0.0;
The variable assignments have no time dimension associated with them. That is, the assignments take their effect immediately. Thus variable has no direct analogue in hardware. Variable can only be used within sequential areas, within a PROCESS, in subprograms (functions and procedures) and not within ARCHITECTURE BODY.
PROCESS(a,b)
VARIABLE val1:STD_LOGIC:=‟0‟;
BEGIN
val1 := a; --variable val1 is assigned the value of signal a.
b <= val1; --signal b is assigned the value of variable val1.
END;
1.3 Signal Class
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An object of class signal can hold or pass logic values, while variables cannot. A signal is a pathway along which information passes from one component in a VHDL description to another. It is analogous to a wire in hardware. It needs not be initalized upon declaration.
SIGNAL identifier [,identifier ...] :TYPE [:=value];
Example:
SIGNAL sigA, sigB: BIT;
Signals are objects whose values may be changed and have a time dimension. Signal values are changed by signal assignment operator (<=).
Example:
a <= b AFTER 10 ns;
c<= d OR e;
The AFTER 10 ns clause in the first example means that signal a will be assigned signal b 10 ns later. In the second example there is no AFTER clause; this is equivalent to AFTER delta. That is, signal assignments are used to represent real circuit phenomena, so if there is no AFTER clause, it is assumed that the signal takes on its new value delta time later. Delta is an arbitrary small time greater than zero.
1.3.1 Signals and Variables
Whenever the code assigns a value to a variable, the simulator simply updates the current value of that variable, as you would expect in any programming language.
But when the code assigns a value to a signal, that assignment is treated differently. The signal has a current value, which is used whenever the signal appears in an expression, and a list of “next values,” each of which consists of a pair of data items: a value for the signal, and the number of simulation cycles after which the signal is actually given that value. So, a signal assignment does not affect the current value of the signal but only the value for a future simulation cycle. At the end of each simulation cycle, the simulator scans through all the signals, and updates each one from its “next values” list for the next cycle that is to occur.
1 LIBRARY IEEE;
2 USE IEEE.STD_LOGIC_1164.ALL;
3
4 ENTITY and_or IS
5 PORT(a,b,c : IN BIT;
6 q: OUT BIT);
7 END and_or;
8 ARCHITECTURE archand_or OF and_or IS
9 SIGNAL temp : BIT;
10 BEGIN
11 temp <= a AND b;
12 q <= temp OR c;
13 END archand_or
2
c
qbtemp
a
TIME cba temp q
0 001 0 0
t 011 0 0
011 1 0 t + ;
011 1 1 t + 2;
The current value of temp is calculated based on the previous values of a and b. The current value of q is
calculated based on the previous values of c and temp.
1.3.2 When to use Variables
Signals assigned to in a process are updated at the end of the process. The signal driver is filled with the
new value when the assignment statement is executed. Then, as the last step before the process is
suspended, that driver is passed to the signal.
Variables, on the other hand, are updated as soon as the variable assignment is executed.
The following process based code implementation of the and_or circuit can’t be implemented.
1 LIBRARY IEEE;
2 USE IEEE.STD_LOGIC_1164.ALL;
3
4 ENTITY and_or IS
5 PORT(a,b,c : IN BIT;
6 q: OUT BIT);
7 END and_or;
8 ARCHITECTURE archand_or OF and_or IS
9 SIGNAL temp : BIT;
10 BEGIN
11 PROCESS(a,b,c)
12 BEGIN
13 temp <= a AND b;
14 q <= temp OR c;
15 END PROCESS;
16 END archand_or
3
TIME cba temp q
0 001 0 0
t 011 0 0
011 1 0 t + ;
Since temp is not in the sensitivity, the event in temp does not cause the activation of q in line 14. In addition, because temp is not in the sensitivity list, this implies that its value must be stored, hence the flip-flop. The problem then is to determine the clock for the flip-flop. Because the process is triggered by any event on a, b, or c, the flip-flop must be active to both a rising and a falling edge for any or all three of the signals. Because very few libraries have flip-flops that are active to edges of a clock, a new function must be built. The edge detector would have to create an active edge for the flip-flop whenever an input signal changes, but this cannot be synthesized. Modify the process sensitivity list to include temp, as follows:
PROCESS(a,b,c,temp);
That is, for a process based description to be synthesized as a combinatorial network, any signal that appears on both the right-hand-side (RHS) and the left-hand-side (LHS) of assignment statements must be included in the process sensitivity definition.
To more efficiently describe intermediate results of operations that are not needed outside of a process you can use variables.
1 LIBRARY IEEE;
2 USE IEEE.STD_LOGIC_1164.ALL;
3
4 ENTITY and_or IS
5 PORT(a,b,c : IN BIT;
6 q: OUT BIT);
7 END and_or;
8 ARCHITECTURE archand_or OF and_or IS
9 BEGIN
11 PROCESS(a,b,c)
12 VARIABLE temp : BIT;
12 BEGIN
13 temp := a AND b;
14 q <= temp OR c;
15 END PROCESS;
16 END archand_or
TIME cba temp q
0 001 0 0
t 011 1 0
011 1 1 t + ;
11.4 Quantity Class
； New Object in VHDL 1076.1
； Represents an unknown in the set of Differential Algebraic Equations (DAEs) implied by the text
of a model
； Continuous-time waveform
； Scalar sub-elements must be of a floating-point type
； Default initial value for scalar sub-elements is 0.0
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； Declaration Syntax:
QUANTITY identifier [,identifier ...] :TYPE [:=value];
； Example:
QUANTITY qc : charge; --coulomb in ELECTRICAL_SYSTEMS package QUANTITY vt : voltage; --volt in ELECTRICAL_SYSTEMS package QUANTITY v: velocity; --m/s in MECHANICAL_SYSTEMS package QUANTITY s: displacement --m in MECHANICAL_SYSTEMS package QUANTITY vout1: REAL :=12.0;
QUANTITY vd ACROSS id THROUGH anode TO cathode;
--defining vd as ACROSS quantity and id as THROUGH quantity flowing from
--anode to cathode
1.5 Terminal Class
； New object in VHDL 1076.1
； Basic support for structural composition with conservative semantics
； Belong to a nature
； Declaration Syntax:
TERMINAL identifier [,identifier ...] :NATURE ;
； Example:
TERMINAL anode, cathode: ELECTRICAL;
； Nature ELECTRICAL is defined in IEEE.ELECTRICAL_SYSTEMS package
1.6 Nature
； Represents a physical discipline or energy domain: electrical, fluidic, mechanical, radiant, thermal
； Has two aspects related to physical effects
; Across: effort like effects (voltage, velocity, temperature, etc.)
; Through: flow like effects (current, force, heat flow rate, etc.)
； A nature defines the types of the across and through quantities incident to a terminal of the nature
； A scalar nature additionally defines the reference terminal for all terminals whose scalar sub-
elements belong to the scalar nature
； A nature can be composite: array or record
; All scalar sub-elements must have the same scalar nature
1.7 Signal Attributes
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； Specific values associated with signals.
； Format:
signal_name' attribute_designator
Example:
clock'ACTIVE
1.7.1 Signal Attributes Which Define Another Signals
1. S'DELAYED(T) is a signal which echoes the value of the prefix signal, delayed by the specified time
factor. If T=0, the value is equal to S after a delta delay (i.e. in the next simulation cycle).
2. S'QUIET(T) is a boolean signal whose value is TRUE if S has not had a transaction (i.e. not active)
for the length of time T. If T=0,FALSE during simulation cycle in which S was assigned to and then
will return to TRUE.
3. S'STABLE(T) is a boolean signal whose value is TRUE if S has not had an event (i.e. not changed
value) for the length of time T. If T=0, the value will be FALSE during the simulation cycle in which
S changed and then will return to TRUE.
4. S'TRANSACTION is a bit signal whose value toggles each time a transaction occurs on S (i.e. S is
active).
1.7.2 Signal Attributes Which Provide Information About Signals
1. S'EVENT is TRUE if an event has occured on S during the current simulation cycle (i.e. if S has
changed value during the cycle).
2. S'ACTIVE is TRUE if a transaction has occured on S during the current simulation cycle.
3. S'LAST_EVENT returns the amount of time which has elapsed since the last event on S (i.e. since S
last changed value).
4. S'LAST_ACTIVE returns the amount of time which has elapsed since the last transaction on S (i.e.
since S was last active).
5. S'LAST_VALUE returns the value of S before the last event on S.
6. S‟DRIVING is false if the current driver of signal S is a null transaction.
7. S‟DRIVING_VALUE returns the current driving value of signal S.
Signal Attribute Supported Attribute for
synthesis
„active No
„delayed[(t)] No
„event Yes
„last_active No
„last_event No
„last_value Yes
„quiet[(t)] No
„stable Yes
„transaction Yes
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1.7.3 Signal Attribute Relationships
An activity is any change on the signal value. A change from `1' to `X' is an example of an activity, and a change from `1' to `1' is an activity. The only criteria is that something happened. However an event requires a change in value of the signal. A change from `1' to `X' is an event, but a change from `1' to `1' is not an event. All events represent activities, but not all activities represent events.
IF S'STABLE is given without a time expression, the expression defaults to 0 ns which means that the check is for stability of the signal at this exact instance in time. This is equivalent to S'EVENT.
S'EVENT is more efficient than S'STABLE. Simulator will take more work to evaluate S'STABLE.
1.7.4 Examples
Example 1: Delayed Signal
sdelay1
clk1
sdelayCLK
ped := 1m
del := 0
periodical := 1
1.2clk1.val
0.6
0.2
-0.2
00.5m1m1.5m2m2.5m3mt [s]
1.2sdelay1.sout
0.8
0.6
0.4
0.2
-0.2
00.5m1m1.5m2m2.5m3mt [s]
ENTITY sdelay IS GENERIC (T: TIME:=1ms ); --Simplorer does not allow changes to TIME par PORT (SIGNAL sin: IN BIT; SIGNAL sout: OUT BIT); END ENTITY sdelay; ARCHITECTURE behav OF sdelay IS
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BEGIN sout <= sin'DELAYED(T); END ARCHITECTURE behav; To change the delay parameter T requires re-compilation of the model. ENTITY sdelay IS GENERIC (T: TIME:=2ms ); PORT (SIGNAL sin: IN BIT; SIGNAL sout: OUT BIT); END ENTITY sdelay; ARCHITECTURE behav OF sdelay IS BEGIN sout <= sin'DELAYED(T); END ARCHITECTURE behav;
1.2sdelay1.sout
0.8
0.6
0.4
0.2
-0.2
00.5m1m1.5m2m2.5m3mt [s]
Example 2: Phase-shifted Clock generation
1.2two_ph_clk1.phase0
0.6
0.2
-0.2
010n20n30n40n50n60n70n80n90n0.1ut [s]
1.2two_ph_clk1.phase1
0.8
0.6
0.4
0.2
-0.2
010n20n30n40n50n60n70n80n90n0.1ut [s]
ENTITY two_ph_clk IS GENERIC(Cycle_Time: TIME:=25 ns); PORT(Phase0,Phase1:OUT BIT); END ENTITY two_ph_clk; ARCHITECTURE behav OF two_ph_clk IS SIGNAL ControlSignal:BIT:='0'; BEGIN ControlSignal <= NOT ControlSignal AFTER Cycle_Time; Phase0 <= ControlSignal; Phase1 <= ControlSignal'DELAYED(Cycle_Time/2); END ARCHITECTURE behav;
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Example 3: Detecting Rising Clock Edge:
clock'EVENT AND clock='1;
(or) NOT clock'STABLE AND clock='1';
(or) NOT clock'QUIET AND clock='1'; (Not supported by Autologic II)
(or) clock‟LAST_VALUE=‟0‟ AND clock=‟1‟; (Preferred Method)
Example 4: Detecting Falling Clock Edge:
clock'EVENT AND clock='0';
(or) NOT clock'STABLE AND clock='0';
(or) clock'LAST_VALUE='1' AND clock='0'; (Preferred Method )
Example 5: Checking Setup and Hold Time of D Flip Flop:
SetupHold
D
clock"STABLE(Hold)
clock
D'STABLE(Setup)
Q
Delay
ENTITY DFF IS
GENERIC(Setup,Hold,Delay:TIME:=0 ns);
PORT(D,clock:IN BIT:='0';Q:OUT BIT:='0';QB:OUT BIT:='1');
BEGIN -- passive process (no signal assignment) only for checking
-- generic constraints.
Check_Setup_and_Hold_Times:
PROCESS(D,clock)
BEGIN
-- Check for setup time
IF NOT clock'STABLE AND clock='0' THEN
ASSERT D'STABLE(Setup)
REPORT "D changed within setup interval"
SEVERITY Warning;
END IF;
-- Check for hold time
IF NOT D'STABLE AND clock='0' THEN
ASSERT clock'STABLE(Hold)
REPORT "D changed within hold interval"
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SEVERITY Warning;
END IF;
--Check for Delay Time
ASSERT (Delay>=Hold)
REPORT “Delay>=Hold Violation”
SEVERITY Warning;
END PROCESS;
END DFF;
ARCHITECTURE one OF DFF IS
SIGNAL value: BIT;
BEGIN
PROCESS(D,clock)
BEGIN
IF((NOT clock'LAST_VALUE) AND (clock = `0')) THEN
value <= D;
END IF;
END PROCESS;
Q <= TRANSPORT value AFTER Delay;
QB <= TRANSPORT NOT value AFTER Delay;
END one;
-- Setup Test Bench
ENTITY tb IS -- no IO
END tb;
ARCHITECTURE setup_one OF tb IS
COMPONENT FF
GENERIC(Setup,Hold,Delay:TIME);
PORT(D,clock: IN BIT;Q,QB:OUT BIT);
END COMPONENT;
FOR u1:FF USE ENTITY WORK.DFF(one);
SIGNAL s1,s2,s3,s4:BIT;
BEGIN
FF_1: FF
GENERIC MAP(2 ns, 1 ns, 5 ns)
PORT MAP(s1,s2,s3,s4);
s1 <= `1' AFTER 13 ns; --must , not ;[only the last one is ;]
`0' AFTER 17 ns;
`1' AFTER 27 ns;
`0' AFTER 35 ns;
s2 <= `1' AFTER 5 ns;
`0' AFTER 15 ns;
`1' AFTER 25 ns;
`0' AFTER 30 ns;
`1' AFTER 35 ns;
`0' AFTER 40 ns;
END setup_one;
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