MLVR REV X8 Design documentation

By Peggy Rogers,2014-04-10 22:23
28 views 0
MLVR REV X8 Design documentation

Design and development of driving and measurement

    hardware for the MLVR HB VS Converter: Rev X8

ENEL664 Special Topic

Hari Kallingalthodi

Student ID number: 39736811


I. Main PCB

1. Driving Circuit

    2. Interface side measurement 3. Output voltage and current measurement

    4. Power supply unit

II. Auxiliary PCB

    1. Fault multiplexer

    2. Future work

III. Reference

IV. Appendix


    The project is to design and implement a simple prototype of MLVR Voltage Source Reinjection Converter in which the drive and measurements are done based on the TMS320F2812 Digital Signal Controller. The design is based on the Rev.X4 design submitted earlier but many changes have been made to the Rev.X4 design for the ease of hardware realization. Two PCB’s are made; one for the signal-level circuitry and DSP

    interface and the other consisting of connectors and system fault indication.

    The design has rolled through from X4 to X8, and the Rev.X8 design is explained in the rest of the report.

I. Main PCB

    1. Driving Circuit

     The drive signal from the JP508 is buffered through an inverting buffer U121 and it is isolated from the high voltage side using a Schmitt trigger output optocoupler. The input side of the optocoupler is operated from a 3.3V power supply and output side is driven from a +15V power supply. Drive signals for the Reinjection and main drives are taken through JP501 which mates with JP8 of the auxiliary board and given to the Semikron driver using BNC connectors.

    2. Interface side measurement and ZCD

     This includes the Zero crossing Detection, interface side measurement of three isolated voltages and three currents in the Phases A, B and C.

Zero crossing detection

    Precision zero crossing detectors come in a fairly wide range of topologies, some interesting, others not. One of the most common and is used for the application. The

    exclusive OR (or XOR) gate makes an excellent edge detector, as shown in the figure below

    The XOR gate will output a 1 only when the inputs are different (i.e. one input must be at logic high (1) and the other at logic low (0v). The resistor and cap form a delay so that when an edge is presented (either rising or falling), the delayed input holds its previous value for a short time. In the example shown, the pulse width is 50ns. The signal is delayed by the propagation time of the device itself (around 11ns), so a small phase error has been introduced. The rise and fall time of the square wave signal applied was 50ns, and this adds some more phase shift.

    Comparators are frequently perceived as devices that crudely express analog signals in digital form - a 1-bit A/D converter. Comparators have two chief requirements ... low input offset and speed. For a zero crossing detector, both of these factors will determine the final accuracy of the circuit. The XOR has been demonstrated to give a precise and repeatable pulse, but its accuracy depends upon the exact time it 'sees' the transition of the AC waveform across zero. This task belongs to the comparator.

    One of the critical factors with the comparator is its supply voltage. Ideally, this should be as low as possible, typically with no more than ?5V. The higher the supply voltage, the further the output voltage has to swing to get from maximum negative to maximum positive and vice versa. While a slew rate of 100V/us may seem high, that is much too slow for an accurate ADC, pulse width modulator or zero crossing detectors.

    At 100V/us and a total supply voltage of 10V (?5V), it will take 0.1us (100ns) for the output to swing from one extreme to the other. To get that into the realm of what is needed, the slew rate would need to be 1kV/us, giving a 10ns transition time.

    The problem is that the output doesn't even start to change until the input voltage passes through the reference point (usually ground). If there is any delay caused by slew rate limiting, by the time the output voltage passes through zero volts, it is already many nanoseconds late. Extremely high slew rates are possible, and there are comparators that are faster than a TTL inverter. Very careful board layout and attention to bypassing is essential at such speeds, or the performance will be worse than woeful. An active low pass filter is used between the input from the transformer and the Comparator U207A. The circuit is shown below.

In the application circuit, the AND gates and the inverter are used to split the + to and

    to + zero crossings. The resistors ensure a proper TTL to CMOS interface. The zero crossings are fed to the capture interrupt input of the DSP. The Schottky diodes provide protection to the capture interrupt input of the DSP

    Transformer Isolated Voltage measurements

    This circuitry measures the voltages at the output of the isolation transformers, scales it and filters the signal to create the input to the absolute value measurement system.

    The absolute value circuitry produces an absolute value signal to be sampled by the ADC input of the DSP. U201A is a scaling amplifier, U201B is a filter, U204A and U204B comprises the absolute value circuitry.

    R252 and R253 will depend on the voltage of the isolation transformer. As a rule of thumb, if it produces 6volts peak to peak, R252 and R253 will be 10k to give a gain of 0.5 for the first scaling stage. Gain of the scaling stage can be calculated by the equation Gain = R204 / (R252+R253).

    R252-C213 and R253-C214 forms a common mode filter to the input. The RC filters on both the inputs are closely matched to avoid tuning the common mode noise into a differential mode noise. These filters reduce the magnitude of the high frequency noise. This will remove some of the common mode rejection requirement of the stage 1 amplifier. The cut off frequency of this filter should be fairly high to have negligible effect on the fundamental signal. The maximum voltage of the stage 1 opamp should be around 2.3Volts. The gain should be adjusted to achieve this maximum output for proper functioning.

    The second opamp is a scaling and filtering opamp. The input to the absolute value system requires a peak to peak of 6V and hence the gain of this stage should be 2.6. The multiturn potentiometer should be used to correct the gain of this stage to the above value. R207 limits the input current to the second stage to about 115μA. C201 will help in making the second stage work as a differential filter. The transfer function of this amplifier will be Vout/Vk = - (R246+R243)/[R207{jω(C201)( R246+R243)+1}]

There is a single pole due to C201, R246 and R243 located at

    {jω(C201)(R246+R243)+1}=0. in this case, the pole occurs between 4kHz and 6kHz.

    The rising edge phase lag due to the inclusion of this pole will be 35μseconds (0.63º) and the falling edge lag will be 41μseconds (0.74º)

    An RC filter comprising of R258 and C210 is used at the ADC output to protect the current into the ADC. This filter has a cut off frequency of 22 kHz and does not have any effect on the phase and magnitude of the system. This will enable fast charging of the ADC sampling capacitors for a fast sampling while maintaining the integrity of the signal with adequate protection. The series schottky diode D1 will ensure that the ADC rail will always be within the voltage limits specified by the DSP data sheet.

    U204A and U204B form the absolute value circuit. The 6V peak to peak signal is converted to a unipolar 3V signal using this circuitry. This method was chosen over DC level shifting as there is no ambiguity around the zero crossings.

     The active clamp (U204B and D225) allows the input voltage (Va) at the non inverting input of U204A to freely vary when it is positive. However when negative it is clamped to the voltage at the non inverting input (Vf) of U204B, which is the return or ground. When Va is greater than Vf, the voltage on the inverting input of the opamp is at a higher potential than the non inverting input. Therefore the output voltage (Vc) of U204B is driven lower to the return, diode D225 is reverse biased and hence the clamp has no effect on the voltage Va. On the other hand when Va is lower than Vf, the non inverting pin is at a higher potential than the inverting input. Therefore Vc is driven higher resulting in the diode D225 being forward biased and Va being clamped to voltage Vf, which is return or ground.

    Va is the reference for the second opamp (U204A) in the absolute value circuit. This opamp works from ?3.3V rails. This opamp works as an inverting amplifier, except that the reference is floating. During the negative half cycle of the incoming waveform, Va is fixed to ground or return. The inverting amplifier inverts the negative half cycles to create positive half cycles of the same magnitude. V output of U204A will be


    During the positive half cycle, Va is not Zero and this equation does not hold.

    Vb = 2Va-Vin. Given that the voltage clamp allows Va to map vin during the positive half cycles they are at the same voltage, hence the above equation can be further simplified for the positive half cycle case.

    Vb = Vin

Current measurements

    The transducer used for isolated current measurement is the RAZTEC RAZC-2. This provides a current measurement range of 0 to ? 100A. The output voltage of the transducer is 2.5V when the input current is zero. The bandwidth of the sensor is 35kHz. The output voltage is scaled to 1.718V at zero current using a 10K and 22K voltage divider circuit so that the dynamic range of the ADC input of the ADC is fully utilized.

    The 3.3V reference voltage for the DSP ADC is externally given using the precision reference LM4120 with a temperature coefficient of +50ppm/?C.

    3. Output Voltage and Current measurement

    R1 is selected to achieve an LED current of about 7-10 mA at the nominal input operating voltage according to the following equation:

If = (VIN/R1)/K1,

    where K1 (i.e., Ipd1/If) of the optocoupler is typically about 0.5%, If current through the LED. R2 is then selected to achieve the desired output voltage according to the equation,


    The purpose of R4 and R6 is to improve the dynamic response (i.e., stability) of the input and output circuits by lowering the local loop gains. R3 and R5 are selected to provide enough current to drive the bases of Q2 and Q4. And R7 is selected so that Q4 operates at about the same collector current as Q2.

    Current is measured using Hall effect current sensor RAZC-2 as in interface side measurement.

    The power supplies for the analog optocouplers (VCC VC1, VCC VC2, VCC VRN1, VCC VRN2 & VCC VRN) are given using five separate 5V plug packs with different references as shown in the schematic.

    4. Power supply unit

    DSP can turn on the power to the driver and measurement boards through the “power enable” signal. This is connected to the base of the transistor Q402 through R413. Relay

    K402 will connect the input power to the regulators.

    Power +/-5V and +/-3.3V supplies for the opamp and the rest of the signal circuitry are generated using two 5V plug-packs and 3.3V voltage regulators. This is enabled using the relay K401 that can be activated by the transistor Q401 and a SPST toggle switch. -3.3V is generated using a LM337 variable negative voltage regulator whose output can be adjusted using 1K trimpot R401.

    Decoupling and energy storage capacitors are used as required. Common mode chokes and differential mode capacitors are used to suppress noise related issues occurring from “snapping on and off” of power semiconductor switches.

    The +15V for Driver Vcc is generated using a 15V power supply for which the relay can be enabled using “Drive power enable signal ” given through P7 in the DSP board.

II. Auxiliary PCB

    1. Fault Multiplexer

    The fault multiplexer accepts the fault signals from the Semikron Driver through the BNC connectors in the auxiliary board and multiplexed it into a single error signal for the DSP interrupt. Driver error signal is negative logic; it gives 15V when there is no error and 0V when an error occurs. When there is no fault all the LED’s will be “on” and when an error occurs the IGBT driver will pull that pin low which causes the LED “off ”. At the same time this causes the optocoupler generate a “HIGH” pulse to the DSP interrupt pin.

    Please note that the fault signals are for mainly for information purposes. The driver would have shut down the IGBT when a fault is flagged. The DSP needs to shut down the drivers and investigate the fault before turning on the drivers again. Simultaneous switching of the high and low drives clear the fault in the driver. This needs to be done in a fashion to avoid cross conduction after consulting the driver data sheets

    Diodes D1 to D10 OR the fault signals and provide it to the interrupt pin of the DSP. This interrupt may be used to shut down all the drivers and the “off ” LED indicates which

    arm is at fault.

    JP8 in the auxiliary board which mates with JP501 in the main board carries all the signals between the main board and the auxiliary board including the fault interrupt signal into the DSP and the power supplies for the parts in the aux-board.

Future Works

    At the time of the preparation of this report PCB sent for manufacturing. Assembling and testing will be done and a test report will be prepared afterwards.


    Electronic circuitry capable of driving, measuring and controlling the MLVR voltage source Reinjection converter is designed and developed. The hardware is designed to suit various configurations of the Reinjection converter. Different configurations of the Reinjection converter may be tested with the prototype board with the measurement, driver and control board designed.


    1. HCNR201 High-linearity analog optocoupler data sheet

    2. TLV2374 data sheet

    3. Semikron- Application note- IGBT Power electronics Teaching system

    4. Raztec RAZC-2 data sheet

    5. H11LS-M optocoupler data sheet

    6. MM74HC4049M inverting buffer data sheet

    7. TI TMS320C28X manuals: SPRU430, SPRU060, SPRU078

    8. Report: Design and development of driving and measurement hardware for the

    MLVR HB VS Converter: Rev X4

    9. 2812 eZDSP tech reference Rev. D


    1. Main Board Schematics Rev. X7

    a. Power circuit

    b. Drive circuit

    c. Interface side measurement

    d. V and I output

    e. PSU

    f. Connectors

    2. Auxiliary Board Schematic

    a. Fault multiplexer and drive signals

Report this document

For any questions or suggestions please email