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GS1559

By Marjorie Cruz,2014-12-23 17:32
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GS1559

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     GS1559 HD-LINX II Multi-Rate Deserializer with Loop-Through Cable Driver

     GS1559 Data Sheet Key Features SMPTE 292M and SMPTE 259M-C compliant descrambling and NRZI ?ú NRZ decoding (with bypass) DVB-ASI sync word detection and 8b/10b decoding auto-configuration for HD-SDI, SD-SDI and DVB-ASI serial loop-through cable driver output selectable as reclocked or non-reclocked dual serial digital input buffers with 2 x 1 mux integrated serial digital signal termination integrated reclocker automatic or manual rate selection / indication (HD/SD) descrambler bypass option user selectable additional processing features including: CRC, TRS, ANC data checksum, line number and EDH CRC error detection and correction programmable ANC data detection illegal code remapping Description The GS1559 is a reclocking deserializer with a serial loop-through cable driver. When used in conjunction with the GS1574 Automatic Cable Equalizer and the GO1555/GO1525* Voltage Controlled Oscillator, a receive solution can be realized for HD-SDI, SD-SDI and DVB-ASI applications. In addition to reclocking and deserializing the input data stream, the GS1559 performs NRZI-to-NRZ decoding, descrambling as per SMPTE 292M/259M-C, and word alignment when operating in SMPTE mode. When operating in DVB-ASI mode, the device will word align the data to K28.5 sync characters and 8b/10b decode the received stream. Two serial digital input buffers are provided with a 2x1 multiplexer to allow the device to select from one of two serial digital input signals. The integrated reclocker features a very wide Input Jitter Tolerance of ?À0.3 UI (total 0.6 UI), a rapid asynchronous lock time, and full compliance with DVB-ASI data streams. An integrated cable driver is provided for serial input loop-through applications and can be selected to output either buffered or reclocked data. This cable driver also features an output mute on loss of signal, high impedance mode, adjustable signal swing, and automatic dual slew-rate selection depending on HD/SD operational requirements. The GS1559 also includes a range of data processing functions such as error detection and correction, automatic standards detection, and EDH support. The device can also detect and extract SMPTE 352M payload identifier packets and independently identify the received video standard. This information is read from internal registers via the host interface port. Line-based CRC errors, line number errors, TRS errors, EDH CRC errors and ancillary data checksum errors can all be detected. A single ??DATA_ERROR?? pin is provided which is a logical 'OR'ing of all detectable errors. Individual error status is stored

    in internal ??ERROR_STATUS?? registers. Finally, the device can correct detected errors and insert new TRS ID words, line-based CRC words, ancillary data checksum words, EDH CRC words, and line numbers. Illegal code re-mapping is also available. All processing functions may be individually enabled or disabled via host interface control. *For new designs use GO1555

     30572 - 7 May 2007 1 of 73 www.gennum.com

     internal flywheel for noise immune H, V, F extraction FIFO load Pulse 20-bit / 10-bit CMOS parallel output data bus 148.5MHz / 74.25MHz / 27MHz / 13.5MHz parallel digital output automatic standards detection and indication 1.8V core power supply and 3.3V charge pump power supply 3.3V digital I/O supply JTAG test interface Available in a Pb-free package small footprint (11mm x 11mm)

     Applications SMPTE 292M Serial Digital Interfaces SMPTE 259M-C Serial Digital Interfaces DVB-ASI Serial Digital Interfaces

     GS1559 Data Sheet Functional Block Diagram

     IOPROC_EN/DIS SMPTE_BYPASS MASTER/SLAVE

     CP_CAP VCO VCO LB_CONT LF VCO_VCC VCO_GND

     FW_EN/DIS

     20bit/10bit

     DVB_ASI

     LOCKED

     RC_BYP

     SD/HD

     IP_SEL

     PCLK

     H

     V

     F

     CD1 CD2

     carrier_detect rclk_ctrl pll_lock LOCK detect

     TERM 1 DDI_1 DDI_1 Reclocker TERM 2 DDI_2 DDI_2 S->P

     smpte_sync_det asi_sync_det

     SMPTE Descramble, Word alignment and flywheel CRC check Line number check TRS check CSUM check ANC data detection

     DATA_ERROR CRC correct Line number correct TRS correct CSUM correct EDH check & correct Illegal code remap

     DOUT[19:0] I/O Buffer & mux FIFO_LD

     K28.5 sync detect, DVB-ASI word alignment and 8b/10b decode (o/p mute) pll_lock rclk_bypass

     CANC YANC

     SDO_EN/DIS SDO SDO Reset RSET HOST Interface / JTAG test

     GS1559 Functional Block Diagram

     RESET_TRST

     CS_TMS SCLK_TCK SDIN_TDI SDOUT_TDO

     JTAG/HOST

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     GS1559 Data Sheet

     Contents

     Key Features ????1 Applications????1 Description ????1 Functional Block Diagram ????2 1. Pin Out ????5 1.1 Pin Assignment ????5 1.2 Pin Descriptions ????6 2. Electrical Characteristics ????16 2.1 Absolute Maximum Ratings ????16 2.2 DC Electrical Characteristics ????16 2.3 AC Electrical Characteristics????18 2.4 Solder Reflow Profiles????20 3. Input/Output Circuits ????21 3.1 Host Interface Map????23 3.1.1 Host Interface Map (R/W Configurable Registers) ????24 3.1.2 Host Interface Map (Read Only Registers) ????25 4. Detailed Description ????26 4.1 Functional Overview ????26 4.2 Serial Digital Input ????26 4.2.1 Input Signal Selection ????27 4.2.2 Carrier Detect Input ????27 4.2.3 Single Input Configuration ????27 4.3 Serial Digital Reclocker ????27 4.3.1 External VCO????28 4.3.2 Loop Bandwidth ????28 4.4 Serial Digital Loop-Through Output ????28 4.4.1 Output Swing ????29 4.4.2 Reclocker Bypass Control ????29 4.4.3 Serial Digital Output Mute????30 4.5 Serial-To-Parallel Conversion ????30 4.6 Modes Of Operation????31 4.6.1 Lock Detect????31 4.6.2 Master Mode????32 4.6.3 Slave Mode????32 4.7 SMPTE Functionality ????34 4.7.1 SMPTE Descrambling and Word Alignment ????34 4.7.2 Internal Flywheel????34 4.7.3 Switch Line Lock Handling????35 4.7.4 HVF Timing Signal Generation ????39 4.8 DVB-ASI Functionality ????41

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     GS1559 Data Sheet

     4.8.1 DVB-ASI 8b/10b Decoding and Word Alignment????41 4.8.2 Status Signal Outputs ????41 4.9 Data Through Mode ????42 4.10 Additional Processing Functions????42 4.10.1 FIFO Load Pulse????42 4.10.2 Ancillary Data Detection and Indication ????43 4.10.3 SMPTE 352M Payload Identifier????46 4.10.4 Automatic Video Standard and Data Format Detection ????47 4.10.5 Error Detection and Indication ????51 4.10.6 Error Correction and Insertion ????57 4.10.7 EDH Flag Detection ????59 4.11 Parallel Data Outputs ????61 4.11.1 Parallel Data Bus Buffers????61 4.11.2 Parallel Output in SMPTE Mode ????62 4.11.3 Parallel Output in DVB-ASI Mode????62 4.11.4 Parallel Output in Data-Through Mode ????62 4.11.5 Parallel Output Clock (PCLK) ????63 4.12 GSPI Host Interface ????64 4.12.1 Command Word Description????64 4.12.2 Data Read and Write Timing ????65 4.12.3 Configuration and Status

Registers ????66 4.13 JTAG????67 4.14 Device Power Up ????68 4.15 Device

    Reset????68 5. Application Reference Design ????69 5.1 Typical

    Application Circuit (Part A) ????69 5.2 Typical Application Circuit

    (Part B) ????70 6. References & Relevant Standards????71 7. Package

    & Ordering Information????72 7.1 Package Dimensions ????72 7.2

    Packaging Data????73 7.3 Ordering Information ????73 8. Revision

    History ????74

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     GS1559 Data Sheet

     1. Pin Out

     1.1 Pin Assignment

     1 A B C D E F G H J K

     LF

     2

     VCO_ VCC

     3

     VCO_ GND

     4

     VCO

     5

     VCO

     6

     NC

     7

     PCLK

     8

     IO_VDD

     9

     10

     DOUT18 DOUT19

     CP_CAP CP_VDD CP_GND

     LB_ CONT

     NC

     NC

     FW_EN/ /DIS

     IO_GND DOUT16 DOUT17

     BUFF _VDD

     PD_VDD

     PD/BUFF _GND

     NC

     NC

     MASTER/ RC_BYP SLAVE

     YANC

     DOUT14 DOUT15

     DDI1

     NC

     NC

     IP_SEL

     DVB_ASI LOCKED

     NC

     CANC

     DOUT12 DOUT13

     DDI1

     TERM1

     NC

     SD/HD

     CORE _GND

     CORE _VDD

     NC

     IO_VDD DOUT10 DOUT11

     CD1

     NC

     NC

     20bit/ 10bit

     CORE _GND

     CORE _VDD

     NC

     IO_GND

     DOUT8

     DOUT9

     DDI2

     NC

     NC

     IOPROC SMPTE_ _EN/DIS BYPASS SCLK _TCK

     RESET _TRST SDOUT _TDO

     NC

     FIFO_LD

     DOUT6

     DOUT7

     DDI2

     TERM2

     NC

     CS_ TMS

     DATA_ ERROR

     H

     DOUT4

     DOUT5

     CD2

     NC

     NC

     NC

     SDO_EN /DIS CD_GND

     SDIN _TDI

     V

     IO_GND

     DOUT2

     DOUT3

     RSET

     CD_VDD

     SDO

     SD0

     JTAG/ HOST

     F

     IO_VDD

     DOUT0

     DOUT1

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     GS1559 Data Sheet

     1.2 Pin Descriptions

     Table 1-1: Pin Descriptions Pin Number

     A1 A2

     Name

     LF VCO_VCC

     Timing

     Analog ?C

     Type

     Output Output Power

     Description

     Control voltage to external voltage controlled oscillator.

    Nominally +1.25V DC. Power supply for the external voltage controlled

    oscillator. Connect to pin 7 of the GO1555/GO1525*. This pin is an output.

    Should be isolated from all other power supplies. *For new designs use

    GO1555

     A3

     VCO_GND

     ?C

     Output Power

     Ground reference for the external voltage controlled oscillator.

    Connect to pins 2, 4, 6, and 8 of the GO1555/GO1525*. This pin is an output. Should be isolated from all other grounds. *For new designs use GO1555

     A4, A5

     VCO, VCO

     Analog

     Input

     Differential inputs for the external VCO reference signal. For single ended devices such as the GO1555/GO1525*, VCO should be AC coupled to VCO_GND. VCO is nominally 1.485GHz. *For new designs use GO1555

     A6, B5, B6, C4, C5, D2, D3, D7, E3, E7, F2, F3, F7, G2, G3, G7, H3, J2, J3, J4, A7

     NC

     ?C

     ?C

     No Connect.

     PCLK

     ?C

     Output

     PARALLEL DATA BUS CLOCK Signal levels are LVCMOS/LVTTL compatible. HD 20-bit mode HD 10-bit mode SD 20-bit mode SD 10-bit mode PCLK = 74.25MHz or 74.25/1.001MHz PCLK = 148.5MHz or 148.5/1.001MHz PCLK = 13.5MHz PCLK = 27MHz

     A8, E8, K8

     IO_VDD

     ?C

     Power

     Power supply connection for digital I/O buffers. Connect to +3.3V DC digital.

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     GS1559 Data Sheet

     Table 1-1: Pin Descriptions (Continued) Pin Number

     A10, A9, B10, B9, C10, C9, D10, D9, E10, E9

     Name

     DOUT[19:10]

     Timing

     Synchronous with PCLK

     Type

     Output

     Description

     PARALLEL DATA BUS Signal levels are LVCMOS/LVTTL compatible. DOUT19 is the MSB and DOUT10 is the LSB. HD 20-bit mode SD/HD = LOW 20bit/10bit

    = HIGH Luma data output in SMPTE mode SMPTE_BYPASS = HIGH DVB_ASI = LOW Data output in Data-Through mode SMPTE_BYPASS = LOW DVB_ASI = LOW HD 10-bit mode SD/HD = LOW 20bit/10bit = LOW Multiplexed Luma and Chroma data output in SMPTE mode SMPTE_BYPASS = HIGH DVB_ASI = LOW Data output in Data-Through mode SMPTE_BYPASS = LOW DVB_ASI = LOW SD 20-bit mode SD/HD = HIGH 20bit/10bit = HIGH Luma data output in SMPTE mode SMPTE_BYPASS = HIGH DVB_ASI = LOW Data output in Data-Through mode SMPTE_BYPASS = LOW DVB_ASI = LOW DVB-ASI data in DVB-ASI mode SMPTE_BYPASS = LOW DVB_ASI = HIGH SD 10-bit mode SD/HD = HIGH 20bit/10bit = LOW Multiplexed Luma and Chroma data output in SMPTE mode SMPTE_BYPASS = HIGH DVB_ASI = LOW Data input in data through mode SMPTE_BYPASS = LOW DVB_ASI = LOW DVB-ASI data in DVB-ASI mode SMPTE_BYPASS = LOW DVB_ASI = HIGH

     B1 B2 B3 B4

     CP_CAP CP_VDD CP_GND LB_CONT

     Analog ?C ?C Analog

     Input Power Power Input

     PLL lock time constant capacitor connection. Normally connected to VCO_GND through 2.2nF. Power supply connection for the charge pump. Connect to +3.3V DC analog. Ground connection for the charge pump. Connect to analog GND. Control voltage to set the loop bandwidth of the integrated reclocker. Normally connected to VCO_GND through 40k??.

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     GS1559 Data Sheet

     Table 1-1: Pin Descriptions (Continued) Pin Number

     B7

     Name

     FW_EN/DIS

     Timing

     Non Synchronous

     Type

     Input

     Description

     CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to enable or disable the noise immune flywheel of the device. When set HIGH, the internal flywheel is enabled. This flywheel is used in the extraction and generation of TRS timing signals, in automatic video standards detection, and in manual switch line lock handling. When set LOW, the internal flywheel is disabled and TRS correction and insertion is unavailable.

     B8, F8, J8 C1 C2 C3 C6

     IO_GND BUFF_VDD PD_VDD PDBUFF_GND MASTER/SLAVE

     ?C ?C ?C ?C Non Synchronous

     Power Power Power Power Input

     Ground connection for digital I/O buffers. Connect to digital GND. Power supply connection for the serial digital input buffers. Connect to +1.8V DC analog. Power supply connection for the phase detector. Connect to +1.8V DC analog. Ground connection for the phase detector and serial digital input buffers. Connect to analog GND. CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to determine the input / output selection for the DVB_ASI, SD/HD, RC_BYP and SMPTE_BYPASS pins. When set HIGH, the GS1559 is set to operate in master mode where DVB_ASI, SD/HD, RC_BYP and SMPTE_BYPASS become status signal output pins set by the device. In this mode, the GS1559 will automatically detect, reclock, deserialize and process SD SMPTE, HD SMPTE, or DVB-ASI input data. When set LOW, the GS1559 is set to operate in slave mode where DVB_ASI, SD/HD, RC_BYP and SMPTE_BYPASS become control signal input pins. In this mode, the application layer must set these external device pins for the correct reception of either SMPTE or DVB-ASI data. Slave mode also supports the reclocking and deserializing of data not conforming to SMPTE or DVB-ASI streams.

     C7

     RC_BYP

     Non Synchronous

     Input /Output

     CONTROL SIGNAL INPUT / STATUS SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. This pin will be an input set by the application layer in slave mode, and will be an output set by the device in master mode. Master Mode (MASTER/SLAVE = HIGH) The RC_BYP signal will be HIGH only when the device has successfully locked to a SMPTE or DVB-ASI compliant input data stream. In this case, the serial digital loop-through output will be a reclocked version of the input. The RC_BYP signal will be LOW whenever the input does not conform to a SMPTE or DVB-ASI compliant data stream. In this case, the serial digital loop-through output will be a buffered version of the input. Slave Mode (MASTER/SLAVE = LOW) When set HIGH, the serial digital output will be a reclocked version of the input signal regardless of whether the device is in SMPTE, DVB-ASI or Data-Through mode. When set LOW, the serial digital output will be a buffered version of the input signal in all modes.

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     GS1559 Data Sheet

     Table 1-1: Pin Descriptions (Continued) Pin Number

     C8

     Name

     YANC

     Timing

     Synchronous with PCLK

     Type

     Output

     Description

     STATUS SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. Used to indicate the presence of ancillary data in the video stream. HD Mode (SD/HD = LOW) The YANC signal will be HIGH when the device has detected VANC or HANC data in the luma video stream and LOW otherwise. SD Mode (SD/HD = LOW) For 20-bit demultiplexed data (20bit/10bit = HIGH), the YANC signal will be HIGH when VANC or HANC data is detected in the luma video stream and LOW otherwise. For 10-bit multiplexed data (20bit/10bit = LOW), the YANC signal will be HIGH when VANC or HANC data is detected anywhere in the data stream and LOW otherwise.

     D1, E1 D4

     DDI1, DDI1 IP_SEL

     Analog Non Synchronous

     Input Input

     Differential input pair for serial digital input 1. CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to select DDI1 / DDI1 or DDI2 / DDI2 as the serial digital input signal, and CD1 or CD2 as the carrier detect input signal. When set HIGH, DDI1 / DDI1 is selected as the serial digital input and CD1 is selected as the carrier detect input signal. When set LOW, DDI2 / DDI2 serial digital input and CD2 carrier detect input signal is selected.

     D5

     DVB_ASI

     Non Synchronous

     Input / Output

     CONTROL SIGNAL INPUT / STATUS SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. This pin will be an input set by the application layer in slave mode, and will be an output set by the device in master mode. Master Mode (MASTER/SLAVE = HIGH) The DVB_ASI signal will be HIGH only when the device has locked to a DVB-ASI compliant data stream. It will be LOW otherwise. Slave Mode (MASTER/SLAVE = LOW) When set HIGH in conjunction with SD/HD = HIGH and SMPTE_BYPASS = LOW, the device will be configured to operate in DVB-ASI mode. When set LOW, the device will not support the decoding or word alignment of received DVB-ASI data.

     D6

     LOCKED

     Synchronous with PCLK

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