GS-18 OFDMA Transceiver Data sheet
Written By : Stuart Bannister Preliminary Version
Table of contents
1 Overview ???? 4 1.1 Introduction ???? 4 1.2 Features ???? 4 1.3 Block Diagrams ???? 5 1.3.1 Internal Architecture ???? 5 1.3.2 System level Architecture ???? 5 Electrical Characteristics ???? 6 SPI Interface ???? 6 3.1 SPI transaction formats ???? 7 3.2 SPI Transfer format ???? 7 3.3 SPI Electrical specifications ???? 8 3.4 Slave Select transaction framing ???? 8 3.5 SPI Register Memory Map ???? 9 Pinouts???? 10 4.1 Brief pin description ???? 10 4.2 Detailed pin description ???? 11 4.2.1 Analog ???? 11 22.214.171.124 Opamps ???? 11 126.96.36.199 DAC ???? 11 188.8.131.52 ADC ???? 11 4.2.2 POWER ???? 12 184.108.40.206 Power 2.5 Volt ????12 220.127.116.11 Power 3.3 Volt ????12 18.104.22.168 I/Os ????13 22.214.171.124 Led indicators ????13 126.96.36.199 Serial peripheral interface (SPI) ????13 188.8.131.52 Special function pins ????13 4.2.3 Oscillator ???? 13 4.3 Pin Diagram ???? 15 Transceiver ???? 15 5.1 General configuration ???? 15 5.1.1 Carrier Arrangement ???? 15 5.1.2 Channel selection ???? 16 5.1.3 Carrier Frequency Control ???? 17 5.1.4 Physical control registers ???? 20 5.2 Transmission ???? 22 5.2.1 Packet Sizing and packet types ???? 22 5.2.2 Band in use Indication ???? 22 5.2.3 Carrier Voltage ???? 23 5.2.4 Transmission Level ???? 24 5.2.5 Transmission Voltage Offset ???? 24 5.2.6 Transmission configuration register ???? 25 5.2.7 Transmission buffering structure???? 25 5.2.8 Send Packet Command ???? 28 5.3 Reception ???? 29 5.3.1 Receiver status ???? 29 5.3.2 Packet Size ???? 29 5.3.3 Receive buffer ???? 29 5.3.4 Noise and Receive Signal Strength indication (RSSI) ???? 30 5.4 Interrupt Signal ???? 30 5.4.1 Interrupt masking ???? 30 5.4.2 Interrupt Sources???? 31 5.5 Addressing resources???? 32
5.5.1 Address Filtering ???? 32 Transmission Scenarios ???? 33 6.1 Brute force transmission ???? 34 6.2 Maximum throughput ???? 34 6.3 Packet by packet ???? 35
The GS-18 is a next generation OFDMA (Orthogonal Frequency Division Multiple Access) power line communications transceiver. It contains a complete packet data modem which utilises a simple PHY (Physical)
layer protocol. This allows the development of proprietary point-to-point and star networks. When combined with an appropriate microcontroller (MCU), the GS-18 provides a costeffective solution for data links and networks. Interface with the MCU is accomplished using a three/ four wire serial peripheral interface (SPI) connection and an interrupt request output which allows for the use of a variety of processors. The SPI port and interrupt request output is used for receive (RX) and transmit (TX) data transfer and control. The software and processor can be scaled to fit applications ranging from simple point-to-point to star networks. Applications may include, but are not limited to, the following: Remote meter reading Energy management (ie lighting, HVAC) The device contains 54 carriers grouped into 18 independent channels. Overall a data rate of up to 175kbps can be achieved with a more robust mode of 125kbps. The transceiver includes an on-chip or external 2.5V core power supply regulation.
Next generation OFDMA transceiver. 54 carriers. 18 independent channels allowing frequency division. Robust channels. Up to 175kbps data rate. BPSK, QPSK selectable modulation. All carriers have selectable frequency in the range of 5kHz to 500kHz giving the ability to avoid strong narrowband interferers or large frequency notches. Independently programmable carrier transmission voltages in 3dB steps. Selectable address filtering to free up SPI bus and masking to allow routing. Inbuilt packet duplicate detection. Excellent near band filtering. Peak to average ratio minimisation even with changing carrier frequencies. Programmable band in use threshold. Ability to implement MAC on internal microprocessor. Ability to buffer 18 whole packets. Each channel can estimate in-band noise content. Each received packet contains an RSSI measurement attached (Receive Signal Strength Indication). Brute force mode for higher reliability. Error correction. Packets protected with CRC. Operates at baseband frequencies for high frequency accuracy. Various power down option to reduce power consumption.
1.3 Block Diagrams
1.3.1 Internal Architecture
The internal structure of the GS-18 is shown below.
Decimation ADC Impulse rejection AGC Deserialiser Filter Bank Demodulator
Sync XTAL1 CLOCK
XTAL2 Timer Microprocessor Frequency Synthesizer Buffer SPI Slave
MISO SCK MOSI SS
DAC Modulator serialiser
Control Registers INTERRUPT
1.3.2 System level Architecture
This a simplified block diagram of a system including the GS-18.
Host processor (Running upper layer protocol)
Power line interface
Figure 2 Figure 2 shows the basic system block diagram for the GS-18 in an application. Interface with the
transceiver is accomplished through a SPI port and interrupt request line. The network and application software (as required) reside on the host processor. The host can vary from a simple 8-bit device up to a sophisticated 32-bit processor depending on application requirements.
2 Electrical Characteristics
Symbol Vdd Vddcore Description Power supply voltage Core power supply voltage Min Typ 3.3V 2.5V Max
Table 1 Electrical Characteristics NOTE: The electrical characteristics are yet to be determined as the chip has not yet been characterized. The above are indication only.
3 SPI Interface
The host microcontroller directs the GS-18, checks its status, and reads/writes data to the device through the SPI port. The transceiver operates as an SPI slave device only. A transaction between the host and the GS-18 occurs as multiple 8-bit bursts on the SPI. The SPI signals are: 1. 2. 3. 4. Slave Select (SS) - A transaction on the SPI port can be framed by the active low SS input signal. A transaction is a minimum of 3 SPI bursts and can extend to a greater number of bursts. SPI Clock (SCK) - The host drives the SCK input to the GS-18 . Master Out/Slave In (MOSI) - Incoming data from the host is presented on the MOSI input. Master In/Slave Out (MISO) - The GS-18 presents data to the master on the MISO output.
A typical interconnection to a microcontroller is shown in Figure 3. <XYZ1234>
Figure 3 Spi Interconnect with host microprocessor
3.1 SPI transaction formats
SPI transactions have three possible formats. Format 1 W/R Bit 1 bit Format 2 W/R Bit 1 bit Format 3 W/R Bit 1 bit Address 7 bits Data Byte 0 8 bits Data Byte 1 8 bits Data Byte N 8 bits Address 7 bits High Data Byte 8 bits Mid Data Byte 8 bits Low Data Byte 8 bits Address 7 bits High Data Byte 8 bits Low Data Byte 8 bits
The W/R Bit tells the state machine if it needs to Write to the
register (Logic 1) or read from the register (Logic 0). The Address is a 7 bit field that tells the state machine which register to read and write from (Memory map is contained in the Memory map section). The two formats represent 16 and 24 bit SPI transfers. 16 bit transfers are used for most commands. Format 3 is only used for packet transfers. Format 3 is designed to minimize the overheads involved in sending and receiving packets.
3.2 SPI Transfer format
The SPI slave contained in the transceiver is designed to work with the widest range of SPI masters. For this reason mode 0 is implemented as it is the most basic mode of SPI transfer and is very widely supported by microcontrollers. Below is a capture of the timing for mode 0 from the ATMEL data sheet.
Figure 2 Figure 2 shows that the SPI settings are CPOL = 0, DORD = 0 and CPHA = 0. This is the defult mode.
3.3 SPI Electrical specifications
1 2 3 4 5
Symbol Tclk Ts Th Tco Tcs
Description SCK clock period Setup time from MOSI output to SCK rising edge Hold time from SCK rising edge to MOSI output Time from SCK rising edge to MISO output Setup time from SS to start of the SPI transaction
Max 100ns (10MHz) TBD TBD TBD TBD
3.4 Slave Select transaction framing
The SPI transceiver has the possibility of getting out of synchronisation if the wrong command is used (ie the transceiver is expecting 24 bits but the host is expecting 16). Also when the transceiver is near power lines transients etc could cause false SPI transitions. To overcome these issues Slave Select (SS) transaction framing can be used. At the end of each command the slave select can be deasserted to reset the SPI Slave. This prevents the master and slave from getting out of sync. The example below shows this behavior.
SCK SS MOSI MISO
Figure 3 Spi timing with SS framing The above example is a write to a register. The SS (Slave Select) signal is driven low telling the SPI slave that a transaction is going to happen. At the end of the transaction the signal is retuned to a high signifying the end of the transaction. Another way to check that the slave is in sync with the master is when data is written the last byte should return hexadecimal ??AA??. This is also demonstrated in figure 3. If the slave is out of sync the transceiver can be reset or the SS can be asserted as previously mentioned.
3.5 SPI Register Memory Map
This table is an overview of all of the registers available to the SPI. All register addresses are in hex. Address 0x20 0x22 0x24 0x26 0x28 0x2A 0x2C 0x30 0x32 0x34 0x36 0x38 0x3A 0x3C 0x40 Register Channel select Channel Frequency Transceiver Control Packet Size / Packet type BIU Threshold Channel Enable BIU Register Transmitter Status Channel Voltage Transmit data Packet Send Transmission coefficients (used for PAR reduction) Transmit buffer selection Transmit voltage (overall) Receiver Status SPI length (bytes) 2 2 2 2 2 3 3 2 2 n 3 2 2 2 2
0x42 0x48 0x50 0x52 0x56 0x60
Channel Noise Received data buffer Interrupt pin mask Interrupt
event register Transmission configuration register Node address (four locations to make 64 bits)
2 n 2 2 2 2
Subnet mask (four locations to make 64 bits)
0x70 0x72 0x74 0x74
AGC control register AGC levels DAC offset Positive DAC offset Negative Table 1 Spi Memory Map
2 2 2 2
Registers are described in depth in the relevant sections.
4.1 Brief pin description
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
OP1_OUT OP1_IN+ OP1_INOP2_OUT OP2_IN+ OP2_INVS25_DAC VD25_DAC VD33_DAC VS33_DAC AOUT_DAC VREG25_ANA VSS_PLL VDD_PLL TXEN AGC_1 VSS_IO VDD_IO VSS_CORE VDD_CORE AGC_0 TX_LED RX_LED RESET INTERRUPT BWSEL
ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG POWER POWER POWER POWER ANALOG POWER POWER POWER CMOS CMOS POWER POWER POWER POWER CMOS CMOS CMOS CMOS CMOS CMOS
A A A A A A P P P P A P P P O O P P P P O O O I O I
Opamp 1 output Opamp 1 non inverting input Opamp 1 inverting input Opamp 2 output Opamp 2 non inverting input Opamp 2 inverting input DAC analog VSS 2.5V DAC analog VDD DAC analog VDD 3.3V DAC analog VSS Analog out DAC Analog Regulator output for decoupling Analog PLL VSS 2.5V Analog PLL VDD Tx Enable I/O AGC 1 I/O IO VSS I/O VDD 3.3V CORE LOGIC VSS CORE LOGIC VDD AGC 0 IO Transmit LED (the same as Tx Enable) Receive LED Transceiver RESET pin (Active high) INTERRUPT pin to be connected to Microprocessor Bandwidth Select Halves bandwidth and power used. (High = half bandwidth)
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
FUNC_TEST SHUTDOWN VDD_IO XIN XOUT VSS_IO SPI_SO SPI_SI SPI_SCK SPI_SS SCAN_ENABLE TEST_MODE VSS_IO VDD_IO VSS_CORE VDD_CORE VS25_ADC VD25_ADC VD33_ADC VS33_ADC VCM_ADC AIN_ADC
CMOS CMOS POWER CMOS CMOS POWER CMOS CMOS CMOS CMOS CMOS CMOS POWER POWER POWER POWER POWER POWER POWER POWER ANALOG ANALOG
I I P I O P O I I I I I P P P P P P P P A A
**** Test only should be tied to VSS_IO SHUTDOWN puts the chip into
minimum power mode. (Active high). I/O VDD 3.3V Oscillator pad in Oscillator pad out I/O VSS SPI slave out SPI slave in SPI clock SPI slave select **** Test only should be tied to VSS_IO **** Test only should be tied to VSS_IO I/O VSS I/O VDD 3.3V CORE LOGIC VSS CORE LOGIC VDD VSS ADC analog power 2.5V VDD ADC analog power 3.3V VDD ADC analog power VSS ADC analog power VREF for ADC ADC analog input
Table 2 Pin configuration
4.2 Detailed pin description
The analog pins are the most sensitive to noise and will affect the performance of the transceiver. Great care should be taken to keep power supplies clean and decoupled. Also analog signals should be kept away from fast switching IO such as the SPI so that noise is not coupled through the PCB.
The GS-18 contains 2 opamps. These opamps are intended to be used for active filtering and gain control for the receiver. The power for the opamps are connected to the analog power pins. OP1_OUT OP1_IN+ OP1_INOP2_OUT OP2_IN+ OP2_INOutput of opamp 1. Non inverting input of opamp 1. Inverting input of opamp 1. Output of opamp 1. Non inverting input of opamp 2. Inverting input of opamp 2.
AOUT_DAC Analog output of the DAC. This is used for transmitting. It is a unipolar output and has an output swing of 0 to 3.3V
VCM_ADC AIN_ADC This pin is the reference for the ADC. It should be decoupled to the analog ground through a 100nF capacitor. Analog input to the ADC. This should be band limited and voltage limited to 3.3V. The incoming signal
should be single ended with an offset of 1.65V. It is envisaged that this input will be driven from the output of the opamp 1.
The following figure shows the internal structure of the power supply for the chip. There are two main voltages 3.3V and 2.5V. The 2.5V is generated inside the chip through linear regulators. There is also an analog and digital power domain. These power domains should be decoupled as much as possible to minimize the influence of digital switching noise on the analog circuitry.
2.5V analog reg
2.5V digital reg
VD33_DAC VD25_DAC DAC
VD33_ADC VD25_ADC ADC
184.108.40.206 Power 2.5 Volt
VS25_DAC VD25_DAC VS25_ADC VD25_ADC VREG25_ANA VSS_PLL VDD_PLL VSS_CORE VDD_CORE 2.5V VSS input power pin for the DAC. 2.5V VSS input power pin for the DAC. 2.5V VSS input power pin for the ADC. 2.5V VSS input power pin for the ADC. Output for 2.5V regulator pin for analog 2.5. 2.5V VSS input power pin for the internal PLL. 2.5V VDD input power pin for the internal PLL. 2.5V VSS pin for the core logic. 2.5V VDD pin for the core logic. Used for decoupling.
220.127.116.11 Power 3.3 Volt
VD33_DAC VS33_DAC 3.3V VDD pin for the DAC. 3.3V VSS pin for the DAC.
VD33_ADC VS33_ADC VSS_IO VDD_IO
3.3V VDD pin for the ADC. This power pin should be as clean as possible as noise will affect the sensitivity of the receiver. 3.3V VSS pin for the ADC. Digital 3.3V VSS input power pin for the I/O. Digital 3.3V VDD input power pin for the I/O.
TXEN AGC_1 AGC_0 RESET INTERRUPT Transmit amplifier enable. This pin is driven to 3.3V when the transceiver is transmitting. Please refer to user manual for details. Please refer to user manual for details. Transceiver reset pin. This pin is active high. The whole chip (including SPI) is reset using this pin. The internal transceiver can be reset through the SPI but the SPI is not reset. This pin is driven low when a transceiver event has occurred. Please refer to user manual for more details on functions.
18.104.22.168 Led indicators
TX_LED RX_LED Transmit LED. Same as the tx_enable pin except with higher drive strength. Receive LED. This LED is asserted when a valid start of packet has been received. The LED does not indicated a correct packet has been received.
22.214.171.124 Serial peripheral interface (SPI)
The SPI interface is used to receive and transmit packets as well as control etc. It can run at a maximum of 10MHz. SPI_SO Slave out SPI_SI Slave in SPI_SCK Spi Clock SPI_SS Slave select pin. When slave select is high the slave out pin is tri-stated.
126.96.36.199 Special function pins
BWSEL SHUTDOWN Bandwidth select. When this pin is high it halves the internal clock so that all 18 channels can operate in the CENELEC
frequency range. It also halves the power consumption. Shutdown pin puts the chip into the lowest power mode possible. It can be used instead of cutting the power to the chip when it is not being used. All settings will be lost as internal power is removed. Shutdown is active high. TEST only ?C Should be tied to VSS_IO TEST only ?C Should be tied to VSS_IO TEST only ?C Should be tied to VSS_IO
FUNC_TEST SCAN_ENABLE TEST_MODE
The oscillator pads are designed to be used with a 10MHz crystal however the Xin pad can be driven with other clock sources. Frequencies below 10MHz can be used but will affect the frequencies of communication. XIN Oscillator input. This can be driven from a crystal, crystal oscillator or microprocessor pin. XOUT Oscillator output pad.
4.3 Pin Diagram
Figure 4 Pin diagram
5.1 General configuration
5.1.1 Carrier Arrangement
Carriers are arranged into 18 groups of 3 carriers. This means that there are a total of 54 carriers. The group of carriers is called a cluster and represents a channel. The Master carrier is the middle frequency of the 3 carriers. Figure 5 demonstrates the relationship between the lower, master and upper carriers in a cluster.
Figure 5 Carrier cluster containing 3 discrete carriers The master carrier can be any of the frequencies given in the frequency control section of the document. The two side carriers are always the frequency above and the frequency below. Each master carrier must be spaced apart at least 3 frequencies apart to allow the operation of the side carriers. The two side carriers can be switched on and off depending on the throughput and reliability needed. If the transceiver is operating in this master only mode then they only need to be one frequency apart. The master carrier contains more information that the side carriers and cannot be turned off.
5.1.2 Channel selection
Channel / Buffer select register Address 0x20 7 6 5 CS5 4 CS4 3 CS3 2 CS2 1 CS1 0 CS0
Register address 0x10 is the Channel / buffer select register. It is used as a pointer to select the channel or buffer which is to be read or configured. It contains 6 bit and the others are unused (CS[5:0]). There are two basic ranges in which it is used. 0 to 17 : This is used for channel or buffer selection. 0 to 53 : This range is used for configuration that selects all carriers. This is only used for transmission coefficient used for reducing the peak to average ratio of the transmission signal.
More information on how to use this register is given in the example transmit and receive scenario sections.
5.1.3 Carrier Frequency Control
Carrier Frequency Control register Address 0x22 7 6 CSEL6 5 CSEL5 4 CSEL4 3 CSEL3 2 CSEL2 1 CSEL1 0 CSEL0
The carrier frequency control register controls the frequency of the 18 master carriers. Firstly thr channel is selected with the channel select register. Then the Carrier control register will change the frequency of that channel. It is an 7 bit register CSEL [6:0] having the range between 0 and 101. The following table shows the possible carrier frequencies that the transceiver can communicate on. Writing a 0 to the register will cause the carrier to be turned off. The table below shows the possible frequencies at which the carriers can operate.
Register Value Frequency Hz
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 9765.63 14648.44 19531.25 24414.06 29296.88 34179.69 39062.5 43945.31 48828.13 53710.94 58593.75 63476.56 68359.38 73242.19 78125 83007.81 87890.63 92773.44 97656.25 102539.06
0 Carrier Off
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57
107421.88 112304.69 117187.5 122070.31 126953.13 131835.94 136718.75 141601.56 146484.38 151367.19 156250 161132.81 166015.63 170898.44 175781.25 180664.06 185546.88 190429.69 195312.5 200195.31