By Kimberly King,2014-12-23 17:30
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     High Performance PFC Controller


     Critical Conduction Mode (CRM) One quadrant multiplier with THD optimizer Low start-up current and operating current Internal start-up timer Internal Min. switching frequency limiting Built-in leading-edge blanking Totem pole output with high state clamping Audio Noise Free Trimmed 1.5% internal band-gap reference Cycle-by-Cycle current limiting Peak current limiting Good Protection Coverage With Under Voltage Lockout (UVLO) with Hysteresis Dynamic and static output over-voltage protection (OVP) Disable function System open loop protection 9.5V to 30V wide operating range of VCC voltage DIP-8 & SOP-8 lead-free package


     PFC pre-regulators for: Electronic Ballast AC/DC SMPS power supply

     General Description

     GS6562 is an active power factor correction (PFC) controller for AC/ DC switching mode power supply applications. It is designed for operating in critical conduction mode (CRM). GS6562 features a quadrant multiplier. It includes a special circuit, able to reduce AC input current distortion, that allows wide-range-mains operation with an extremely low THD, even a large load range. GS6562 also features an internal start-up time for stand-alone applications, Zero Current Detector (ZCD), peak current sense comparator, and a totem pole output. GS6562 ensures safe operation with complete protections against all the fault conditions. Built-in protection circuitry includes system over voltage protection (OVP), VCC under voltage lockout (UVLO), cycle-by-cycle current limiting, multiplier output clamping for limiting maximum peak switch current, system open loop protection, and gate drive output clamping for external power MOSFET protection. In GS6562, a two-step OVP which contains dynamic OVP and static OVP enables to safely handle over voltage either occurring at start-up or resulting from load disconnection.



     High Performance PFC Controller

     Pin Assignment & Description ??DIP-8L & SOP-8L ??






     Inverting Input of Error Amplifier. Connected to Resistor Divider from system Output. This pin is used to sample the information on the output voltage of the PFC pre-regulator. Out of Error Amplifier. A feedback compensation network is placed between this pin and the INV pin to achieve stability of the voltage control loop. Input of Multiplier. Connected to line voltage after bridge diodes via a resistor divider to provide sinusoidal reference voltage to the current loop. Current Sense Input pin. Zero Current Detection Input. When activated, a new switching cycle starts. If it is connected to GND, the device is disabled. Ground pin Gate driver output. Drive the power MOSFET. DC power supply voltage.




     3 4 5 6 7 8

     Typical Application Circuit


     GS6562 Block Diagram

     High Performance PFC Controller



     Absolute Maximum Ratings


     VCC IZCD INV COMP CS MULT Tj Tsgt Lead Temperature


     DC Supply voltage Zero Current Detector Max. Current


     30 50mA(source) -10mA(sink)


     V mA

     Analog inputs ?? outputs

     -0.3 to 7.0


     Min/Max Operating Junction Temperature Min/Max Storage Temperature (Soldering, 10secs)

     -20 to 150 -55 to 150 260

     ?æ ?æ ?æ


     GS6562 Electrical Characteristics

     (Ta=27?ã unless otherwise noted) C

     Symbol Pin Parameter

     High Performance PFC Controller

     Test conditions After Turn On

     Min 11 11 8.5


     Max 30 13 10.5

     Unit V V V V V ?ÌA mA mA mA mA ?ÌA

     SUPPLY VOLTAGE SECTION Vcc 8 Operating Range 8 UVLO??OFF?? UVLO 8 UVLO??ON?? Hys 8 Hysterics Vz 8 Zener Voltage Supply current section Icc-start 8 Start-up Current Quiescent Current, Iq 8 No Switching Operating Supply Icc 8 Current

     Icc=5mA Vcc=11V Vcc=14.5V CL=1nF@ 70KHz In OVP condition Vpin1=2.7V Vpin5?Ü150mv Vcc=14.5V Vpin5?Ü150mV, Vcc<Vccoff

     12 9.5 2.5 33 35 3.0 4.0 1.4 1.1 35

     70 4.0 5.5 2.1 2.1 70



     Quiescent Current

     ERROR AMPLIEIER SECTION Voltage Feed- back Vinv 1 Input Threshold Vinv 1 Line Regulation Iinv 1 Input Bias Current Gv Voltage Gain Gd Gain Bandwidth Source Current Icomp 2 Sink Current Upper Clamp Voltage Vcomp 2 Lower Clamp Voltage MULTIPLIER SECTION Linear Operating Vmult 3 Range ?Vcs/ Output Max. Slope ?Vmult K Gain CURRENT SENSE COMPARATOR Current Sense VCS 4 Reference Clamp Input Bias Current Ics 4 Delay to Output Td(H-L) 4

     Vcc=14.5V 12V<Vcc<28V IDD=10mA Open loop Vcomp=3.6V, Vinv=2.4V Vcomp=3.6V, Vinv=2.6V Isource=0.5mA Isink=0.2mA


     2.5 2 -0.1 80 1.2 -6 6 5.2 2.25

     2.55 5 -1

     V mV ?ÌA dB MHz mA mA V V

     60 -2 2

     -10 10

     Vcomp=3.0V Vmult=from 0 to 0.5V Vcomp=Upper clamp Voltage Vmult=1V, Vcomp=3.5V Vmult=2.5V Vcomp=Upper Clamp Voltage VCS=0

     0 to 3.5 1.65 0.50 1.6 1.9 0.65 1.7 200 0.80 1.8 0.1 450

     V V/V 1/V V ?ÌA ns


     GS6562 Electrical Characteristics (Continued)

     (Ta=27?ã unless otherwise noted) C

     Symbol Pin Parameter

     High Performance PFC Controller

     Test conditions





     ZERO CURRENT DETECTOR Input Threshold 5 Voltage Rising Edge Vzcd Hysteretic Upper Clamp Vzcd 5 Voltage Lower Clamp Vzcd 5 Voltage Izcd 5 Input Bias Current Source Current Izcd 5 Capability Sink Current after Izcd 5 Disable Vdis 5 Disable threshold Restart Current Izcd 5 after Disable GATE DRIVE SECTION VOL 7 Low Output Voltage VOH 7 High Output Voltage Rising Time Tr 7 Falling Time Tf 7 Voclamp 7

     1.9 0.5 Izcd=2.5mA Izcd=-2.5mA 1.0V?ÜVzcd?Ü4.5V -3 3 150 Vzcd<Vides Vcc>Vccoff Vcc=14.5V, Io=100mA Vcc=14.5V, Io=100mA C1=1000pF,10 ??90% C1=1000pF,10 ??90%


     V V 6.3 0.8 V V ?ÌA -5 10 mA mA mV ?ÌA V V ns ns V

     5.1 0.4

     5.7 0.65 2





     1.5 8 80 30 16 150 70 18

     Output Clamp Vcc=28V Voltage OUTPUT OVER VOLTAGE SECTION Dynamic OVP Iovp 2 Triggering Current Static OVP Threshold START UP TIMER Tstart Re-start timer period SYSTEM OPEN LOOP PROTECTION COMPARATOR System Open Loop Protection Vth-ol Comparator Threshold

     40 2.3 70 150 300

     ?ÌA V ?Ìs



     V 1.5


     GS6562 Operation Description

     GS6562 is a highly integrated power factor correction (PFC) controller IC that operates in critical conduction mode (CRM). It turns on MOSFET when the inductor current reaches zero and turns off MOSFET when the inductor current meets the desired input current reference voltage as shown below.

     High Performance PFC Controller

     AC ripple of the line voltage and get a good power factor. It is usually realized with a capacitor which connected between the inverting input and EA output.


     The one quadrant multiplier output limits the MOSFET peak current with respect of the system output voltage and the AC half wave rectified input voltage. Through controlling the CS comparator threshold as the AC line voltage traverses sinusoidally from zero to peak line voltage,

    the PFC pre-regulator??s load appears to be resistive to the AC line. In GS6562, the two inputs for the multiplier are designed to achieve good linearity over a wide dynamic range to represent an AC line free from distortion. One is connected to an external resistor divider which monitors the rectified AC line voltage, the other one is internal driven by a DC voltage which is the difference between error amplifier output COMP and reference voltage, Vref. The equation (1) below describes the relationship between multiplier output and its inputs.

     Inductor Current Waveform

     In this way, the input current waveform follows that the input voltage, therefore a good factor is obtained.

     Startup Operation

     VDD is the power supply terminal for the GS6562. The startup resistor from the rectified high voltage DC rail supplies current to the VDD bypass capacitor. During startup, the GS6562 typically draws only lower than 70uA, so that VDD could be quickly charged up above UVLO threshold. A large value startup resistor can be used to minimize the power loss in standby mode. As soon as VDD is beyond the UVLO(OFF), the chip will begin to start.

     Vm = K ?Á VMULT ?Á (VCOMP ? Vref )


     K : Multiplier Gain VMULT : Voltage at Pin 3(MULT) VCOMP : Error Amplifier Output Voltage (COMP)

     Vref : Internal 2.5V Reference Voltage

     Error Amplifier

     The sensed and divided output voltage is feedback to the error amplifier inverting input (INV). This voltage is compared to an internal reference voltage (2.5V) to set the regulation on output voltage. The EA output is internally connected to the multiplier input and externally connected for loop compensation. Generally, the system loop bandwidth is set below 20 Hz to suppress the

     Zero Current Detection

     GS6562 operates as a critical conduction mode controller. It can perform zero current detection by using an auxiliary winding of the inductor. When the stored energy is fully released to the output, the voltage at ZCD will decrease. Once the inductor current reaches ground level, the polarity of the voltage across the winding is reversed. When the ZCD input falls below 1.4V,



     the zero current detector will be triggered to turn on the power MOSFET and start a new switching cycle. To prevent false tripping, 0.5V hysteresis is provided. The zero current detector input is protected internal by two clamps. The upper 5.7V clamp prevents input over voltage

    breakdown while the lower 0.65V clamp prevents substrate injection.

     High Performance PFC Controller

     transient protection and static OVP for output stead-state protection. In an output transient OVP event, currents in proportion to ??V flows into Error Amplifier output COMP through compensation network. When this current reaches 32?ÌA, the output of multiplier is forced to decrease and on-time of MOSFET is reduced. When current continues to exceed 40?ÌA, the power MOSFET is turned off until the current falls below 10?ÌA. In this way, the system output cannot reach to a very high value. When OVP event lasts long enough, the Error Amplifier output, COMP, will saturate and stay low. Static OVP comparator is activated and power MOSFET Gate is off when COMP voltage is dropped below 2.30V. Normal operation is resumed when Error Amplifier goes back to its linear region after output voltage drops.

     Current Sensing

     GS6562 detects primary MOSFET current from the CS pin, which is not only for the peak current mode control but also for the cycle-by-cycle current limit. The multiplier output voltage is compared with this sense voltage through an internal comparator to limit the inductor current. The maximum voltage threshold of the current sensing pin is set as 1.7V. Thus the MOSFET peak current can be calculated as:

     I peak (max) =

     1.7V RS


     System open loop protection

     GS6562 offers a function of system open loop protection. If INV pin is below 0.25V with 50mV hysteresis, the switching will turn off. In this way, the system output voltage cannot increase too high (only the rectified line voltage), and the pre-regulator will be protected from damage.

     An internal RC filter is connected to the CS pin which smoothes the switch-on current spike. The remaining switch-on spike is blanked out via an internal leading edge blanking (LEB) circuit. Another extra function of LEB is that it limits the system minimum on time, thus the THD of system at light load will be decreased.

     Disable function

     A disable function is provided in GS6562. When the ZCD pin is below 0.25V?? GS6562 is disabled and some internal functional blocks are tuned off. The operation current is very small under this condition until the ZCD pin is released.

     Protection Controls

     A lot of good protections features have been implemented in GS6562 to prevent the power supply from being damaged caused by fault conditions. These protection features contains VCC under voltage lockout (UVLO),

    cycle-by-cycle current limiting, peak current limiting, output dynamic and static over-voltage protection (OVP), and output gate clamp.

     Gate Drive Output

     GS6562 contains a singe totem-pole output stage designed specifically for a direct drive of power MOSFET. With a 1nF load, the rise time of the drive output is 80ns and the fall time is 30ns. The built-in 16V clamp at the gate output protects the MOSFET gate from high voltage stress.

     Over Voltage Protection

     Limited by low loop bandwidth setting, detection of output OVP could become very slow in regular approach. GS6562 offers two level OVP protection including dynamic OVP for output fast


     GS6562 Typical Performance Characteristics

     High Performance PFC Controller

     Multiplier Characterization 1.8 1.6 Multiplier Output(V) 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 0.5 1 1.5 2 2.5 Vmult(V) 3 3.5 4 4.5 COMP=2.8V COMP=3.0V COMP=3.2V COMP=3.5V COMP=4.0V COMP=4.5V COMp=5.0V


     GS6562 Package Dimensions


     High Performance PFC Controller



     A A1 b c D E e F H L ?È?


     1.346 0.101

     Millimeter Typ.


     1.752 0.254


     0.053 0.004

     Inch Typ.


     0.069 0.010

     0.406 0.203 4.648 3.810 1.016 5.791 0.406 0?ã 4.978 3.987 1.524 6.197 1.270 8?ã 0.183 0.150 0.040 0.228 0.016 0?ã

     0.016 0.008 0.196 0.157 0.060 0.244 0.050 8?ã

     1.270 0.381X45?ã

     0.050 0.015X45?ã




     High Performance PFC Controller



     A A1 A2 b b1 D E E1 e L eB ?È?

     Millimeters Min.

     0.381 3.175 3.302 1.524 0.457 9.017 6.223 2.921 8.509 0? 9.271 7.620 6.350 2.540 3.302 9.017 7? 3.810 9.525 15? 0.115 0.335 0? 6.477 0.245 10.160 0.355 3.429

     Inches Max.

     5.334 0.015 0.125 0.130 0.060 0.018 0.365 0.300 0.250 0.100 0.130 0.355 7? 0.150 0.375 15? 0.255 0.400 0.135







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