DOC

Investigation

By Carl Mitchell,2014-02-18 10:49
7 views 0
Investigation

    Investigation

    94JournalofOoc~uaUniversity(Eng.Ed.)Vo1.24.No.1(2007) InvestigationofImprovedSignalProcessandControlCircuitforColor

    PDP

    QIuSong(邱崧),QIURun-he(仇润鹤),HUWen-jing(胡文静)h,ZHANGTian-qiao(张天

    ),

    LIHuang(李煌)

    1SchoolofInformation,Science&TechnoIogy,EastChinaNormalUniversity,Shangh

    ai200062,China

    2CollegeofInformationScienceandTechnology,DonghuaUniversity,Shanghai201620,C

    hina

    Abstract:Wepresentallalternativecurrent-plasmadisplay panel(AGPDP)signalprocessandcontrolcircuitthat fmfiIIsthesignalprocessandtransformfunction.We proposedanoveldrivinglogicalwaveformgeneratorbasedon theSICIinterface,whichCallreal-timeaajusttheparameters tooptimizeperformanceofthePDPandfacilitatethe researchandtest.Theuseofnestingstate-machineand parameterizeddesignnotonlyimprovestheresource utilization,butalsomakesitefficientandreadable.The designhasbeenwritteninsynthesizableVerilogandfully verifaxtusingXilinxFdeviceandappliedin42inAC-

    PDPmodule.

    Keywords:AC_PDP,Verilog,SCJinterface,FPGA,

    nestirIgState-Machine.

    cLcnmnber:TN915.04Documentcode:A

    ArtideID:1672522O(2OO7)O1009405

    ThecircuitadoptedtheImprovedADSmethod[1Jto overcometheDFCproblemcausedbythetemporalnon? uniformityoftheconventional8-subfieldsADSmethod. Theuppertwosub-fieldsaredividedintofoursub-fields, andtheorderisrearrangedinto64:32:32:4:1:2:8 :16:32:64.ThelightemissiondiagraminFig.1(a) indicatesthatonesub-fieldinvolvesthreeperiods.PDP cellsareself-erasedischarginginthe''resetperiod"and selectivedischarginginthe"addressperiod".Afterwards? allselectedcellsaresustaindischargingtogethertoproduce lightinthe"sustainperiod".However?theproportionof theseperiodsaffectsthePDP'sdisplayperformance includingcontrastratio,luminance,etc.Whendeveloping andtestingthePDP,wehopetoreal-timeadjustmany parameterstogetthebestperformance.Therefore,in additiontoprocessingthevideosignalintotheAC-PDP signalandcontrollingthehighvoltagedrivers(HVD),the circuitweproposedaimstoadjusttheparametersonlinein ordertocomparethedisplayeffectunderallkindsof drivingwaverapidly,andtopickuptheoptimizedone. ResetPehod?AddPeriodSustainPeriod

    (a)LightemissiondiagramoftheimprovedADSmethod (b)TypicalthreeelectrodesAC*PDPdriversystem Fig.1DrivingmethodandsystemforAC-PDP

    Fig.1(b)showsatypical42-inAC?PDPusedasthe testpane1withaconventionalthree.electrodecoplanar structure.ThFeekindsofelectrodes,namedascommon (X)electrode,(Y)scanelectrodeandaddress(A) electrode.arerespectivelyconnectedtoHVDincludingX sustaindriver,YscandriverandAaddressdriver.

    PopularlycomposedofhighpowerMOSFETorspecialIC. HVDworksasIeve1.shiftertoconvertTTLOrCMOS signalstohighvoltage(HV)pulses.The2556sticksofA electrodesaredrivenby40chipsofdriverICupd16337.X electrodesaredirectlydrivenbyXsustaindriver(M_0lsFEr switchcircuit).The480sticksofYelectrodesaredriven by8chipsofICupd163o5.

    1ArchitectureandM0duIarizatiOn

    Thecircuitiscomposedoftwoparts,oneissignal processingandconvertingunit,theotherisHVDcontrol unit.Duringthereset,addressandsustainperiod,HVD Receiveddata:20060726

    Foundationitem..TheAMFoundationofShanghai(No.0206) CorrespondenceshouldbeaddressedtoHUWen-jing,Dr.,E-mail:inforsystem@126.com

    JournalofDonghuaUniversity(EngEd.)Vo1.24?No.1(2007)95 controlunitorderlyoutputsthe,LorCMOSsignalsthat

    controltheHVDtoapplyhighvoltagepulsestodisplay electrodes.Besides,signalprocessingandconvertingunit convertstheinputrawdigitalvideosignalwithVGA852×

    480definitionat37.997MHZtoACPDPsub-fieldsignal

    datawhicharestoredintheframememory.Thenthe storeddataarewithdrawnfromtheframememoryand regulatedintoproperformatdatafortheaddressdrivers R

    

    (8bi

    .

    t)

,Lul?,

    DC

    

    LK37

    

    .

    - 997M1v……

    B^NK

    Sdranl#l

    Sdranl#2

    data

    reorganIZIng

    andstoring

    nlodule

    thatapplythedatapulsestoAaddresselectrodesand accomplishtheaddressingoperationcooperatingwiththe HVDcontrolunit.

    AccordingtotheprincipleofTop?Downdesignmethod, wedividedthecircuitintothefollowingfourtopmodules: DHtareorganizingandstoringnxxtule,Data?r~ldingand addressingmodule,SCIinterfacemodule?HVDtiming sequencegeneratormodule,asshowedinFig.2. SClinterface

    nlodulc

    Data.reading

    and

    addressing

    nlodule

    L

    Signalprocessingandcon\e

Register

    

    s

    c.I

    

    Adldressdisplaydata4bitX20

    Conlpntcr

    Paltlbrill

    rtingunitttVDcontrolunit

    Fig.2Architectureandmodulesdiagramofthecircuit 2SignalProcessingandConvertingUnit Therearetwomodulesinthesignalprocessingand convertingunit:Datareorganizingandstoringmoduleand Data.readingandaddressingmodule.

    2.1Data-reorganizingandstoringmodule Fig.3showsthatthismoduleconsistsofaFinite StateMachine(FSM)(INTERFACE

    FSM),aDFC

    R(gNt)

    G(8bit)

    IstgroupIstgroup

    RlI7..0

    GlI7..0

    RlI9..0

    GII9..0

    block,aBitseparatedblockandaSD_WRITERblock VideoInterfaceCircuitoutputsparallel24bitRGB

    videodatainsynchronismwithdataclock(DCLK). INTERFACEFSMsamplesthreegroupsof24bitdata

    eachcycleandoutputsthemasfourbytespergroup.

    DFCblockprocessesvideodatatodecreaseDFCeffect. Thisblockutilizesalookuptabletotransformonebyte to10bits.whichmeansitoutputs40bitdataper

    group.

    BSBl

    64*l0bit

    B(gbit)R2[7

    "

    0R219"01SAM

    ResetjIIBLANKLIsA?lLE2

    ._

    DCLKSHIFT__CLKOUT}?L

    VSYCSHIFTEN?I(

    I

    

    vaIld

    __

    ?

    0

    ?

    Melllreadelk

    Fig.3FunctionalblockdiagramofDatareorganizingandstoringmodule Fournestingstate..machinesandacoupleofBit- separatedbuffers(BSB)makeupoftheBit.separated block.Fig.4showsthestatediagramofthesenesting state-machines.TheSHIFF

    EN(shiftenin)and

    VSYCsignalsstartSAMPLE1FSMthatreceives16 groupsof40-bitdatafromtheuppercircuitandputs themintoBSB1whosestructureis64groupsof10-bit

    parallel-in/serialoutShift-register.Wechoosetheinput SHIFT_

    CLK

    OUTasthestateshiftclock.Oncejumping

    toST16,SAMPLE1startstheSHIFT1FSMand

    SAMPLE2FSM.SAMPLE2samplesthedataintothe BSB2inthesamewayasSAMPLE1does.Whereas. SHIFT1FSMshiftsouttenbatchesof64bitdata

    representingtendifferentsubfieldsjntheBSBfromleft

    toright.Likewise.whentheSAMPLE2finishes,it startsSAMPLElandSHlFT2FSM.

    e

    hgv".n

    V(

    96JournalofOonghuaUniversity(Eng.Ed)Vo1.24.No.1(2007) Fig.4Statediagramofthenestingstate-machines IftheValidsignalissettohigh,theSDWRITER

    startstoreceivetenbatchesof64.bit.widedataandwrite themseparatelyintenblocksoftheframememorywhose databuswidthisalso64bit.Thus,thedataaresortedby thesubfieldintheframememory.

    elk

    n

    ThecircuitiscompatibletogeneralSDRAMinterfaceto makeitreusable2.WechoosetheSDRAM(HY57V64322O) whoseorganizationis2MX32bitsandwedoublethedatabus tO64bitsbycouplingtwochips.Forthe852×480panel,

    thereare4O×64bitSdataforonerOWinonesubfield. EVEN0DDEVEN0DD

AddrbuflbrI.D2ll5JDlll5jD2lOjDlL0J

    D2l3lJD131j02l1tijDll6j

    D2L47JD1L47JD2L32jDll32J

    SUB_SYNCD2L63JDlI63J1)2L48JD1L48J AddrSd

    SD_CS\

    g-_orF==》删盯///PDl6337

    4bit#l

    SDSYNC\Addrbuflferl._-Read

    done#2

    SDCLK,

    ShifI.

    PULSEaddr

    FSMShifIfsm

    RESET,

    done

    /,4i._#39

    CLK,l-_buflfer:O

    #40ADDRCLK

    Fig.5Datar?dillgandaddress.mgmodule

    2.2Data-ingandaddressingrrule

    111ismodulec0nsistSofthef0llowingblocks:anFSM, anaddr

    generatOr,anSDreader,ashift-addr-fsm

    cOntainingAddressBuffer.Fig.6sh0wsthestatediagram OftheFSM.OncetheSDGbitisdetected,theFSM iumpstoS1whereawholerowofvideodataintheframe memOryisreadintOAddresSBufferbycarryingOutthe taSkSDreader.SDCSsignalSelectSthetargetSDI chip.Theaddr_generatOrgenerateSthememOryaddress

    f0rSD_readerbyc0untingtheSDSYNC,SUB_SYNCand VSYCsigna1.Finishingthepr0cesS,SDl_readerwillSetthe read.donesignalhigI1.0ncethePlSE.bitg0eshigIl,the

    FsMiumpStos2wheretheshift.addr.fsmstartstotransfer thedatafr0mtheA-ddresSBuffertOtheA-ddresSDrivers. WhentheAddressBufferisclearedOut,Shift.addr.fsmwill SettheShifLdOnebithigh,andthemainFsMwillreturn tOtheinitialstateSO.

    S

    Fig.6StatediagramOftheFsM

    1shift-addfsrn?ntro1s4Ochips0fIC'upm6337'

    ,?hOse.mterfIdceisgenerallyad0pt.dinP)P'saddng

    JournalofDonghuaUniversity(Eng.Ed.)Vo/.24,No.1(2007)97 circuit.DoubleDat|IRatedesignisemployedinorderto decreasethecircuit'speripheralports,111etwoadjacentICs shareonedatachannel,sodatabusiscutbyhalfandthe transferclock(ADDRCLK)maintainsthehighestfrequency 20MHz.TheAddressBufferiscomposedof20groupsof4×

    32bitl~ralle1.in/seria1.outshift.registerblock.Wemustmix everytwochips'databit?by-bit.Ontherisingedgeofthe ADDR_CLK,shift.addr-fsmoutputsthedataofoddchips.To thecontrary,itsendsouttheoneofevenchips,

    3HVDControIUnit

    TheHV.driverwaveformisnormallycontrolledonthe basisofthesignalgeneratedfromthisunit.Inthe conventionalWavegenerationcircuit,thedatarepresentinga signalassociatedwithawaveformandthecontrolthereofare storedinaROMforeach"basicperiodofwavegeneration,and thedatathusstoredintheR0Maresequentiallyreadoutto

    generatewaveform['.However.thenloreprecise waveformrequirestheuseofaROMofhigherspeedand volume.Also,111ebiggestproblemisthatit'sdifficultto revisetheR0Mvaluewhenthecircuitisworking.Forthese reasons,wediscloseanewdesignforthisunitusingtheFSM designandSCIinteffacemodule,

    3.1sCIinterfacemodule

    SCIinterfaceissimpleanduniversaltoimplementthe datacommunicationwithafewwirestosavethepins resourceoftheF]PGA.Fig.7showstheblockdiagramof theSCIinterfacemodule.

    Fig.7BlockdiagramoftheSCIinterfacemodule

    Aftertheinternalcontrolregistersareinitialized,the SCIinterfacestartstoreceivethedatastreamfromtheupper- machine(PCorMCU)throughtheRXD.TheSCI

    interfacetransforms.theserialbitstreamtoparallelbytes. Thesebytesmakeupofthedataframeaccordingtothe frameprotocolwemade.Then,thedataframesare receivedandtranslatedbytheregisterscontroller.Ifsome errorshappen,theerrorbitwillbesethigh,andthe registerscontrollerwillsendbacktwochars'a7a7'to requesttheuppermachinetorestartthetransferprocess. Whentheregisterscontrolleracquiresthetargetregister value,itwon'twritethemdirectlytothetargetregisters buttothetempregisters,Onceallthetempregistersare filled,allthetempregistersaretobemovedtothetarget registerstillthenextVSYCcomes.

    WeutilizePCastheuppermachinetoeditthe

    registersdatabecausetheuserinterfaceissofriendlythat wecanrapidlyadjustthedatausingtheprogramcodedin

Report this document

For any questions or suggestions please email
cust-service@docsford.com