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MI2000

By Nathan Harris,2014-04-27 20:15
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MI2000

    MICRON CONFIDENTIAL AND PROPRIETARYPRELIMINARY‡

    MT9D001 1/2-INCH CMOS ACTIVE-

    Micron Part Number: MT9D001C1ST

    PIXEL DIGITAL IMAGE

    SENSOR

    •Pixel Size and Type: 4.2µm x 4.2µm active pixel Introduction

    photodiode-type The MT9D001 is a UXGA-format ?-inch CMOS

    •Color Filter Array: R, G, and B primary color filters active-pixel digital image sensor. The active imaging

    Optical Format: 1/2 inch pixel array is 1600H x 1200V. It incorporates sophisti-

    •Supply Voltage: .0V to .6V, . V nominal cated camera functions on-chip such as windowing,

    •Frame Rate: 20 fps at UXGA resolution; 0 fps at column and row skip mode, and snapshot mode. It is

    SXGA; 100 fps at VGA; 250 fps at CIF; programmable programmable through a simple two-wire serial inter-

    •Data Rate: 48 MHz at 48 MHz master clock face.

    •Responsivity (green pixels): 1.8 V/lux-sec with The sensor can be operated in its default mode or

    source illumination @ 550nm programmed by the user for frame size, exposure, gain

    •SNRmax: >42dB setting, and other parameters. The default mode out-

    Dynamic Range: >60dB puts a UXGA-size image at 20 frames per second. An

    •Shutter: Electronic rolling shutter (ERS) on-chip analog-to-digital converter (ADC) provides 10 0 •Window Size: UXGA, programmable to any smaller bits per pixel. Frame- and line-valid signals are output

    0 format (SXGA. XGA, SVGA, VGA, CIF, QVGA, QCIF, on dedicated pins, along with a pixel clock that is syn-

    2 etc.) chronous with valid data.

    / •Programmable Controls: Gain, frame rate, frame

    size 2 Features

    •ADC: On-chip 10-bit serial •Array Format (4: ): 1,600H x 1,200V (1920,000 active 1

    •Power Consumption: 250mW nominal at maximum pixels). Total (incl. dark pixels): 1,6 2H x 1,224V /

    data rate, . V (1,997,568 pixels)

     •Package: 48-pin CLCC

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    MDM Source Numbermi2000.fm-Rev. A 5/0 EN1?200 Micron Technology, Inc.

    ‡PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY

    MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.

    MICRON CONFIDENTIAL AND PROPRIETARYPRELIMINARY

    Figure 1: Pin Out Diagram

    X

    PI A

    ND D A_ ND ND ND AT LK

    NCDG VD NCNCVA AG AG SC SD NCDG

    12 45648474645444 7 NC 42 STANDBY

    8 41 TRIGGER FRAME_VALID

    9 40 NC LINE_VALID

    10 9 STROBE RESET_BAR

     8 11 NC DGND

     7 NC VDD 12 48-PIN CLCC

    1 6 DOUT<9> OE_BAR

    14 5 NC DOUT<8>

     4 AGND DOUT<7> 15

    0 16 DOUT<6> VAA

    0 17 2 AGND DOUT<5>

    2 18 1 AGND PIX_CLK / 192021222 242526272829 0

    2 > > > > > INNC NCVAA NDVDDND 1 <0 <1 <2 < <4 K_ AG DG / UT UT UT UT UT CL

    DO DO DO DO DO

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    MDM Source NumberMicron Technology, Inc., reserves the right to change products or specifications without notice.mi2000.fm-Rev. A 5/0 EN2?200 Micron Technology, Inc.

    MICRON CONFIDENTIAL AND PROPRIETARYPRELIMINARY

    Figure 2: Sensor Architecture Block Diagram

    VAA_PIX

    e s

    Pixel Array ver cod 1224 Dri 1600x1200 De w w 16 2 x 1224 Full Ro Ro

    16 2

    PGA1x-15x + Column S/H 10 Bit ADC 7 bit

    Column Decode

    0 Row andColumn Gain ControlADC TimingOffset Correction STROBE 0 Timing Register Bank Dead PixelCorrection CLK_IN DOUT<0:9> Windowing 2 SCLK Serial PIX_CLK Exposure Gain Interface SDATA Biasing / LINE_VALID

    Digital Block FRAME_VALID 2

    1

    /

    OE_BAR RESET_BAR TRIGGER STANDBY VDD DGND VAA AGND t

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    MDM Source NumberMicron Technology, Inc., reserves the right to change products or specifications without notice.mi2000.fm-Rev. A 5/0 EN ?200 Micron Technology, Inc.

    MICRON CONFIDENTIAL AND PROPRIETARYPRELIMINARY

Pin Description

    Table 1: Pin Descriptions

    PIN

    NUMBERSSYMBOLTYPEDESCRIPTION

    1VAAPIXSupplyAnalog Pixel Power: Provide power supply for pixel array, . V? 0. V 2NC-No Connect: These pins must be left unconnected

     NC-No Connect: These pins must be left unconnected

    4VDDSupplyDigital Power: Provide power supply for digital block, . V ? 0. V 5DGNDSupplyDigital Ground: Provide isolated ground for digital block

    6NC-No Connect: These pins must be left unconnected

    7STANDBYInputStandby: Activates (HIGH) standby mode, disables analog bias circuitry for power

    saving mode

    8TRIGGERInputTrigger: Activates (HIGH) snapshot sequence

    9NC-No Connect: These pins must be left unconnected

    10RESET_BARInputReset: Activates (LOW) asynchronous reset of sensor. All registers assume factory defaults

    11NC-No Connect: These pins must be left unconnected

    0 12NC-No Connect: These pins must be left unconnected

    0 1 OE_BARInputOutput Enable: OE_BAR when high places outputs DOUT<0-9>, FRAME_VALID,

    2 LINE_VALID, PIX_CLK and STROBE into a tri-state configuration

    / 14NC-No Connect: These pins must be left unconnected

    2 15AGNDSupplyAnalog Ground: Provide isolated ground for analog block and pixel array

    1 16VAASupplyAnalog Power: Provide power supply for analog block, . V ? 0. V.

    / 17AGNDSupplyAnalog Ground: Provide isolated ground for analog block and pixel array 18AGNDSupplyAnalog Ground: Provide isolated ground for analog block and pixel array 19NC-No Connect: These pins must be left unconnected t

    f 20VAASupplyAnalog Power: Provide power supply for analog block, . V ?0. V. 5 a 21AGNDSupplyAnalog Ground: Provide isolated ground for analog block and pixel array

    r 22VDDSupplyDigital Power: Provide power supply for digital block, . V ?0. V

    D 2 DGNDSupplyDigital Ground: Provide isolated ground for digital block 24DOUT <0>OutputData Out: Pixel data output bits 0, DOUT<9> (msb), DOUT<0> (lsb) 25DOUT <1>OutputData Out: Pixel data output bits 1, DOUT<9> (msb), DOUT<0> (lsb) 26DOUT <2>OutputData Out: Pixel data output bits 2, DOUT<9> (msb), DOUT<0> (lsb) 27DOUT < >OutputData Out: Pixel data output bits , DOUT<9> (msb), DOUT<0> (lsb) 28DOUT <4>OutputData Out: Pixel data output bits 4, DOUT<9> (msb), DOUT<0> (lsb) 29CLK_INInputClock In: Master clock into sensor (48MHz maximum)

     0NC-No Connect: These pins must be left unconnected

     1PIX_CLKOutputPixel Clock: Pixel data outputs are valid during falling edge of this clock

    Frequency = (Master Clock)

     2DOUT <5>OutputData Out: Pixel data output bits 5, DOUT<9> (msb), DOUT<0> (lsb)

     DOUT <6>OutputData Out: Pixel data output bits 6, DOUT<9> (msb), DOUT<0> (lsb)

     4DOUT <7>OutputData Out: Pixel data output bits 7, DOUT<9> (msb), DOUT<0> (lsb)

     5DOUT <8>OutputData Out: Pixel data output bits 8, DOUT<9> (msb), DOUT<0> (lsb)

     6DOUT <9>OutputData Out: Pixel data output bits 9, DOUT<9> (msb), DOUT<0> (lsb)

     7VDDSupplyDigital Power: Provide power supply for digital block, . V ?0. V

     8DGNDSupplyDigital Ground: Provide isolated ground for digital block MDM Source NumberMicron Technology, Inc., reserves the right to change products or specifications without notice.mi2000.fm-Rev. A 5/0 EN4?200 Micron Technology, Inc.

    MICRON CONFIDENTIAL AND PROPRIETARYPRELIMINARY

Table 1: Pin Descriptions (Continued)

    PIN

    NUMBERSSYMBOLTYPEDESCRIPTION

     9STROBEOutputStrobe: Output is pulsed high to indicate sensor reset operation of pixel array

    has completed

    40LINE_VALIDOutputLine Valid: Output is pulsed high during line of selectable valid pixel data (see

    reg #0x20 for options)

    41FRAME_VALIDOutputFrame Valid: Output is pulsed high during frame of valid pixel data

    42NC-No Connect: These pins must be left unconnected

    4 DGNDSupplyDigital Ground: Provide isolated ground for digital block

    44NC-No Connect: These pins must be left unconnected

    45SDATAInput/ Serial Data: Serial data bus, requires 1.5kohm resister to . V for pullup

    Output

    46SCLKInputSerial Clock: Clock for serial interface

    47AGNDSupplyAnalog Ground: Provide isolated ground for analog block and pixel array

    48AGNDSupplyAnalog Ground: Provide isolated ground for analog block and pixel array

    0

    0

    2

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    2

    1

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    D MDM Source NumberMicron Technology, Inc., reserves the right to change products or specifications without notice.mi2000.fm-Rev. A 5/0 EN5?200 Micron Technology, Inc.

    MICRON CONFIDENTIAL AND PROPRIETARYPRELIMINARY

    Pixel Data Format

    setting the sensor to raw data output mode (Reg0x20, Pixel Array Structure

    bit 11 = 1). There are 1609 columns by 1209 rows of The MT9D001 pixel array is 16 2 columns by 1224

    optically active pixels, which provides a four-pixel rows. The first 20 columns and the first 8 rows of pixels

    boundary around the UXGA (1600 x 1200) image to are optically black, and can be used to monitor the

    avoid boundary affects during color interpolation and black level. The last columns and the last 7 rows of

    correction. pixels are also optically black. The black row data is

    used internally for the automatic black level adjust-

    ment. However, the black rows can also be read out by

    Figure : Pixel Array Description

    (0, 0)

    8 black rows

    UXGA (1600x1200) + 4 pixel boundary for

    color correction black columns 20 black columns + additional active column 0 + additional active row

    = 1609x1209 active pixels 0

    2

    /

    7 black rows 2 (16 1, 122 )

    1

    / The MT9D001MT9D001 uses a Bayer color pattern. pixels. Likewise, even numbered columns have green

    Even numbered rows have green and red color pixels, and blue color pixels, and odd numbered columns

    and odd numbered rows have blue and green color have red and green color pixels. t

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    column readout direction

    black pixels

    Pixel

    (8, 20)

    G R G R G R G

    row B B G G B B G

    readout G R G R G R G direction

    B B G G B B G

    G R G R G R G

    B B G G B B G

    MDM Source NumberMicron Technology, Inc., reserves the right to change products or specifications without notice.mi2000.fm-Rev. A 5/0 EN6?200 Micron Technology, Inc.

    MICRON CONFIDENTIAL AND PROPRIETARYPRELIMINARY

    grammable through Reg0x05 and Reg0x06, respec- Output Data Format

    tively. LINE_VALID is high during the shaded region of The MT9D001 image data is read out in a progres-

    the figure. FRAME_VALID timing is described in the sive scan. Valid image data is surrounded by horizontal

    next section. and vertical blanking, as shown in Figure 5. The

    amount of horizontal and vertical blanking is pro-

    Figure 5: Spatial Illustration of Image Readout

    .................. P0,0 P0,1 00 00 00 00 00

    00 P1,0 P1,1 P1,2.....................................P1,n-1 P1,n .................. 00 00 00 00 00 P0,2.....................................P0,n-1 P0,n 00

    VALID IMAGE HORIZONTAL BLANKING

    0

    .................................. Pm-1,0 Pm-1,1 m-1,n-1 Pm-1,n 00 00 00 00 00 ..................................... P 0 ... .............................. Pm,0 Pm,1 00 00 00 00 ..................................... 2 ....... m,n-1P Pm,n 00 00 00 ..................................... / 00 00 00 00 00 00 00 00 ..................................

    ..................................... 00 00 00 00 ... 00 00 00 00 00 00 00 00 ..................................2 00 00 00 00 ... 1

    VERTICAL BLANKING VERTICAL / HORIZONTAL BLANKING /

     ..................................... 00 00 00 00 00 .................................. 00 00 00 t 00 ... ..................................... 00 00 00 00 00 00 00 00 00 .................................. 00 00 f 00 00 00 00 ... 5 a

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    MDM Source NumberMicron Technology, Inc., reserves the right to change products or specifications without notice.mi2000.fm-Rev. A 5/0 EN7?200 Micron Technology, Inc.

    MICRON CONFIDENTIAL AND PROPRIETARYPRELIMINARY

Output Data Timing

    The data output of the MT9D001 is synchronized

    with the PIX_CLK output. When LINE_VALID is HIGH,

    one 10-bit pixel datum is output every PIX_CLK

    period.

    Figure 6: Timing Example of Pixel Data

    .....

    LINE_VALID

    .....

    PIX_CLK

    ..... Blanking Blanking Valid Image Data

    P0 P1 P2 P P4 Pn-1 Pn 0 ..... DOUT9-DOUT0 (9:0) (9:0) (9:0) (9:0) (9:0) (9:0) (9:0) 0

    2

    / The rising edges of the PIX_CLK signal are nomi- PIX_CLK is HIGH while master clock is HIGH and then

    2 nally timed to occur on the rising DOUT edges. This LOW while master clock is LOW. It is continuously

    1 allows PIX_CLK to be used as a clock to latch the data. enabled, even during the blanking period.

    / DOUT data is valid on the falling edge of PIX_CLK. The

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    f Figure 7: Row Timing and FRAME_VALID/LINE_VALID Signals

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    r . . .

    D FRAME_VALID

    . . . LINE_VALID

    . . .

    P1 A Q A Q A P2 Number of master clocks

    MDM Source NumberMicron Technology, Inc., reserves the right to change products or specifications without notice.mi2000.fm-Rev. A 5/0 EN8?200 Micron Technology, Inc.

    MICRON CONFIDENTIAL AND PROPRIETARYPRELIMINARY

Frame Timing Formulas

    Table 2: Frame Timing

    PARAMETERNAMEEQUATION (MASTER CLOCK)DEFAULT TIMING

    AActive Data Time(Reg0x04 + 1)1600 pixel clocks

    = . µs

    P1Frame Start Blanking(258)258 pixel clocks

    = 5. 7µs

    P2Frame End Blanking(Reg0x05 - 17) 100 pixel clocks

    (minimum (Reg0x05 value = 19) = 2.08µs

    Q = P1 + P2Horizontal Blanking (241 + Reg0x05) 58 pixel clocks

    (minimum Reg0x05 value = 19) = 7.46µs

    A+QRow Time(244 + Reg0x04 + Reg0x05)1958 pixel clocks

    = 40.79µs

    VVertical Blanking(Reg0x06 + 1) x (A + Q) 50,908 pixel clocks

    (minimum Reg0x06 value = 15) = 1.06µs

     Nrows * (A+Q)Frame Valid Time(Reg0x0 + 1) x (A + Q) 2, 49,600 pixel clocks

    = 48.95ms

    FTotal Frame Time(Reg0x0 + 1 + Reg0x06 + 1) * (A + Q)2,400,508 pixel clocks 0

    = 50.01ms 0

    2 Sensor timing is shown above in terms of pixel clock blanking rows (Reg0x0 + 1 + Reg0x06 + 1). If this is not

    / and master clock cycles (please refer to Figure6). The the case, the number of integration rows must be used recommended master clock frequency is 48 MHz. The instead to determine the frame time, as shown in 2 vertical blank and total frame time equations assume Table . 1 that the number of integration rows (bits 1 through 0 / of Reg0x09) is less than the number of active plus

    t Table : Frame Time - Master Clock f

    5 a PARAMETERNAMEEQUATION (MASTER CLOCK)DEFAULT TIMING r V’Vertical Blanking (long integration time)(Reg0x09 Reg0x0 ) * (A + Q)50,908 pixel clocks

    D = 1.06µs F’Total Frame Time (long integration time)(Reg0x09 + 1) * (A + Q)2,400,508 pixel clocks

    = 50.01ms MDM Source NumberMicron Technology, Inc., reserves the right to change products or specifications without notice.mi2000.fm-Rev. A 5/0 EN9?200 Micron Technology, Inc.

    MICRON CONFIDENTIAL AND PROPRIETARYPRELIMINARY

Serial Bus Description

    Registers are written to and read from the MT9D001 incremented after every 16 bits is transferred. The data through the two-wire serial bus. The sensor is a serial transfer is stopped when the master sends a no- slave and is controlled by the clock (SCLK), which is acknowledge bit.

    driven by the two-wire serial master. Data is trans-

    ferred into and out of the MT9D001 through the data Bus Idle State

    (SDATA) line. The SDATA line is pulled up to . V off- The bus is idle when both the data and clock lines chip by a 1.5K resistor. Either the slave or master are HIGH. Control of the bus is initiated with a Start device can pull the SDATA line down the serial proto- bit, and the bus is released with a Stop bit. Only the col determines which device is allowed to pull the master can generate the start and stop bits. SDATA line down at any given time.

    Start Bit Protocol The start bit is defined as a HIGH to LOW transition The two-wire serial bus defines several different of the data line while the clock line is HIGH. transmission codes, as follows:

    •A start bit Stop Bit •The slave device 8-bit address

    The stop bit is defined as a LOW to HIGH transition •An (no) Acknowledge bit

    of the data line while the clock line is HIGH. •An 8-bit message

    •A Stop bit 0

    Slave Address 0

    The 8-bit address of an serial device consists of 7 Sequence 2 bits of address and 1 bit of direction. A 0 in the LSB of A typical read or write sequence begins by the mas- / the address indicates write-mode, and a 1 indicates ter sending a start bit. After the start bit, the master 2 read-mode. sends the slave device's 8-bit address. The last bit of 1 the address determines if the request will be a read or a / Data Bit Transfer write, where a “0” indicates a write and a “1” indicates

    a read. The slave device acknowledges its address by One data bit is transferred during each clock pulse,

    t sending an acknowledge bit back to the master. which is provided by the master. The data must be sta-

    f If the request was a write, the master then transfers ble during the HIGH period of the serial clock it can 5 a the 8-bit register address to which a write should take only change when the serial clock is LOW. Data is r place. The slave sends an acknowledge bit to indicate transferred 8 bits at a time, followed by an acknowl- that the register address has been received. The master edge bit. D then transfers the data 8 bits at a time, with the slave

    sending an acknowledge bit after each 8 bits. The Acknowledge Bit

    MT9D001 uses 16 bit data for its internal registers, thus The master generates the acknowledge clock pulse. requiring two 8-bit transfers to write to one register. The transmitter (which is the master when writing, or After 16 bits are transferred, the register address is the slave when reading) releases the data line, and the automatically incremented, so that the next 16 bits are receiver indicates an acknowledge bit by pulling the written to the next register address. The master stops data line LOW during the acknowledge clock pulse. writing by sending a start or stop bit.

    A typical read sequence is executed as follows. First No-Acknowledge Bit the master sends the write-mode slave address and 8- The no-acknowledge bit is generated when the data bit register address just as in the write request. The

    line is not pulled down by the receiver during the master then sends a start bit and the read-mode slave

    acknowledge clock pulse. A no-acknowledge bit is address. The master then clocks out the register data 8 used to terminate a read sequence. bits at a time. The master sends an acknowledge bit

    after each 8-bit transfer. The register address is auto-

    MDM Source NumberMicron Technology, Inc., reserves the right to change products or specifications without notice.mi2000.fm-Rev. A 5/0 EN10?200 Micron Technology, Inc.

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