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PCA8574_IcpdfCom_1206548

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PCA8574_IcpdfCom_1206548

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     PCA8574/74A

     Remote 8-bit I/O expander for I2C-bus with interrupt

     Rev. 02 ?ª 14 May 2007 Product data sheet

     1. General description

     The PCA8574/74A provide general purpose remote I/O expansion for most microcontroller families via the two-line bidirectional I2C-bus (serial clock (SCL), serial data (SDA)). The devices consist of an 8-bit quasi-bidirectional port and an I2C-bus interface. The PCA8574/74A have low current consumption and include latched outputs with 25 mA high current drive capability for directly driving LEDs. The PCA8574/74A also possess an interrupt line (INT) that can be connected to the interrupt logic of the microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C-bus. The internal Power-On Reset (POR) initializes the I/Os as inputs.

     2. Features

     I I I I I I I I I I I 400 kHz I2C-bus interface 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os 8-bit remote I/O pins that default to inputs at power-up Latched outputs with 25 mA sink capability for directly driving LEDs Total package sink capability of 200 mA Active LOW open-drain interrupt output 8 programmable slave addresses using 3 address pins Readable device ID (manufacturer, device type, and revision) Low standby current (10 A max.) 40 ?ãC to +85 ?ãC operation ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 I Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA I Packages offered: DIP16, SO16, TSSOP16, SSOP20

     3. Applications

     I I I I I LED signs and displays Servers Industrial control Medical equipment PLCs

     NXP Semiconductors

     PCA8574/74A

     Remote 8-bit I/O expander for I2C-bus with interrupt

     I Cellular telephones I Gaming machines I Instrumentation and test measurement

     4. Ordering information

     Table 1. Ordering information Topside mark PCA8574D PCA8574AD PCA8574N PCA8574AN PCA8574 PA8574A PCA8574 PCA8574A SSOP20 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4

mm plastic shrink small outline package; 20 leads; body width 4.4 mm

    SOT403-1 SOT266-1 DIP16 plastic dual in-line package; 16 leads (300

    mil); long body SOT38-1 Package Name SO16 Description plastic small

    outline package; 16 leads; body width 7.5 mm Version SOT162-1 Type number

    PCA8574D PCA8574AD PCA8574N PCA8574AN PCA8574PW PCA8574APW PCA8574TS

    PCA8574ATS

     5. Block diagram

     PCA8574 PCA8574A

     INT AD0 AD1 AD2 SCL SDA INPUT FILTER

     INTERRUPT LOGIC

     LP FILTER

     I2C-BUS CONTROL

     SHIFT REGISTER

     8 BITS

     I/O PORT

     P0 to P7

     write pulse read pulse VDD VSS POWER-ON RESET

     002aac677

     Fig 1. Block diagram of PCA8574/74A

     PCA8574_PCA8574A_2

     NXP B.V. 2007. All rights reserved.

     Product data sheet

     Rev. 02 ?ª 14 May 2007

     2 of 27

     NXP Semiconductors

     PCA8574/74A

     Remote 8-bit I/O expander for I2C-bus with interrupt

     write pulse Itrt(pu) data from Shift Register D FF CI S power-on

    reset D FF read pulse CI S Q Q

     100 A

     IOH

     VDD

     IOL

     P0 to P7

     VSS

     data to Shift Register

     002aac109

     to interrupt logic

     Fig 2. Simplied schematic diagram of P0 to P7

     6. Pinning information

     6.1 Pinning

     PCA8574N PCA8574AN

     AD0 AD1 AD2 P0 P1 P2 P3 VSS 1 2 3 4 5 6 7 8

     002aac679

     16 VDD 15 SDA 14 SCL AD0 13 INT 12 P7 11 P6 10 P5 9 P4 AD1 AD2 P0 P1 P2 P3 VSS 1 2 3 4 5 6 7 8

     002aac678

     16 VDD 15 SDA 14 SCL 13 INT 12 P7 11 P6 10 P5 9 P4

     PCA8574D PCA8574AD

     Fig 3. Pin conguration for DIP16

     Fig 4. Pin conguration for SO16

     PCA8574_PCA8574A_2

     NXP B.V. 2007. All rights reserved.

     Product data sheet

     Rev. 02 ?ª 14 May 2007

     3 of 27

     NXP Semiconductors

     PCA8574/74A

     Remote 8-bit I/O expander for I2C-bus with interrupt

     INT SCL AD0 AD1 AD2 P0 P1 P2 P3 VSS 1 2 3 4 5 6 7 8

     002aac941

     1 2 3 4 5 6 7 8 9

     20 P7 19 P6 18 n.c. 17 P5 16 P4 15 VSS 14 P3 13 n.c. 12 P2 11 P1

     002aac680

     16 VDD 15 SDA 14 SCL 13 INT 12 P7 11 P6 10 P5 9 P4

     n.c. SDA VDD AD0 AD1 n.c. AD2

     PCA8574PW PCA8574APW

     PCA8574TS PCA8574ATS

     P0 10

     Fig 5. Pin conguration for TSSOP16

     Fig 6. Pin conguration for SSOP20

     6.2 Pin description

     Table 2. Symbol AD0 AD1 AD2 P0 P1 P2 P3 VSS P4 P5 P6 P7 INT SCL SDA VDD Pin description for DIP16, SO16, TSSOP16 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Description address input 0 address input 1 address input 2 quasi-bidirectional I/O 0 quasi-bidirectional I/O 1 quasi-bidirectional I/O 2 quasi-bidirectional I/O 3 supply ground quasi-bidirectional I/O 4 quasi-bidirectional I/O 5 quasi-bidirectional I/O 6 quasi-bidirectional I/O 7 interrupt output (active LOW) serial clock line serial data line supply voltage

     PCA8574_PCA8574A_2

     NXP B.V. 2007. All rights reserved.

     Product data sheet

     Rev. 02 ?ª 14 May 2007

     4 of 27

     NXP Semiconductors

     PCA8574/74A

     Remote 8-bit I/O expander for I2C-bus with interrupt

     Pin description for SSOP20 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Description interrupt output (active LOW) serial clock line not connected serial data line supply voltage address input 0 address input 1 not connected address input 2 quasi-bidirectional I/O 0 quasi-bidirectional I/O 1 quasi-bidirectional I/O 2 not connected quasi-bidirectional I/O 3 supply ground quasi-bidirectional I/O 4 quasi-bidirectional I/O 5 not connected quasi-bidirectional I/O 6 quasi-bidirectional I/O 7

     Table 3. Symbol INT SCL n.c. SDA VDD AD0 AD1 n.c. AD2 P0 P1 P2 n.c. P3 VSS P4 P5 n.c. P6 P7

     PCA8574_PCA8574A_2

     NXP B.V. 2007. All rights reserved.

     Product data sheet

     Rev. 02 ?ª 14 May 2007

     5 of 27

     NXP Semiconductors

     PCA8574/74A

     Remote 8-bit I/O expander for I2C-bus with interrupt

     7. Functional description

     Refer to Figure 1 ??Block diagram of PCA8574/74A??.

     7.1 Device address

     Following a START condition, the bus master must send the address of the slave it is accessing and the operation it wants to perform (read or write). The address of the PCA8574/74A is shown in Figure 7. Slave address pins AD2, AD1, and AD0 choose 1 of 8 slave addresses. To conserve power, no internal pull-up resistors are incorporated on AD2, AD1, and AD0. Address values depending on AD2, AD1, and AD0 can be found in Table 4 ??PCA8574 address map?? and Table 5 ??PCA8574A address map??. Remark: When using the PCA8574A, the General Call address (0000 0000b) and the Device ID address (1111 100Xb) are reserved and cannot be used as device address. Failure to follow this requirement will cause the PCA8574A not to acknowledge.

     slave address A6 A5 A4 A3 A2 A1 A0 R/W

     programmable

     002aab636

     Fig 7. PCA8574/74A address

     The last bit of the rst byte denes the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation. When AD2, AD1 and AD0 are held to VDD or VSS, the same address as the PCF8574 or PCF8574A is applied.

     7.1.1 Address maps

     Table 4. A6 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 PCA8574 address map A5 A4 0 0 0 0 0 0 0 0 A3 0 0 0 0 0 0 0 0 A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Address 20h 21h 22h 23h 24h 25h 26h 27h

     PCA8574_PCA8574A_2

     NXP B.V. 2007. All rights reserved.

     Product data sheet

     Rev. 02 ?ª 14 May 2007

     6 of 27

     NXP Semiconductors

     PCA8574/74A

     Remote 8-bit I/O expander for I2C-bus with interrupt

     PCA8574A address map A5 1 1 1 1 1 1 1 1 A4 1 1 1 1 1 1 1 1 A3 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Address 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh

     Table 5. A6 0 0 0 0 0 0 0 0

     8. I/O programming

     8.1 Quasi-bidirectional I/O architecture

     The PCA8574/74A??s 8 ports (see Figure 2) are entirely independent and can be used either as input or output ports. Input data is transferred from the ports to the microcontroller in the Read mode (see Figure 9). Output data is transmitted to the ports in the Write mode (see Figure 8). This quasi-bidirectional I/O can be used as an input or output without the use of a control signal for data directions. At power-on the I/Os are HIGH. In this mode only a current source (IOH) to VDD is active. An additional strong pull-up to VDD (Itrt(pu)) allows fast rising edges into heavily loaded outputs. These devices turn on when an output is written HIGH, and are switched off by the negative edge of SCL. The I/Os should be HIGH before being used as inputs. After power-on, as all the I/Os are set HIGH, all of them can be used as inputs. Any change in setting of the I/Os as either inputs or outputs can be done with the write mode. Remark: If a HIGH is applied to an I/O which has been written earlier to LOW, a large current (IOL) will ow to VSS.

     8.2 Writing to the port (Output mode)

     To write, the master (microcontroller) rst addresses the slave device. By setting the last bit of the byte containing the slave address to logic 0 the write mode is entered. The PCA8574/74A acknowledges and the master sends the data byte for P7 to P0 and is acknowledged by the PCA8574/74A. The 8-bit data is presented on the port lines after it has been acknowledged by the PCA8574/74A. The number of data bytes that can be sent successively is not limited. The previous data is overwritten every time a data byte has been sent.

     PCA8574_PCA8574A_2

     NXP B.V. 2007. All rights reserved.

     Product data sheet

     Rev. 02 ?ª 14 May 2007

     7 of 27

     NXP Semiconductors

     PCA8574/74A

     Remote 8-bit I/O expander for I2C-bus with interrupt

     SCL

     1

     2

     3

     4

     5

     6

     7

     8

     9 data 1 data 2

     slave address SDA S A6 A5 A4 A3 A2 A1 A0 0 START condition R/W

     A P7 P6 1 P4 P3 P2 P1 P0 A P7 0 P5 P4 P3 P2 P1 P0 A P5 acknowledge from slave P5 acknowledge from slave tv(Q) acknowledge from slave

     write to port tv(Q) DATA 1 VALID DATA 2 VALID

     data output from port P5 output voltage

     P5 pull-up output current INT

     Itrt(pu) IOH

     td(rst)

     002aac120

     Fig 8. Write mode (output)

     8.3 Reading from a port (Input mode)

     All ports programmed as input should be set to logic 1. To read, the master (microcontroller) rst addresses the slave device after it receives the interrupt. By setting the last bit of the byte containing the slave address to logic 1 the Read mode is entered. The data bytes that follow on the SDA are the values on the ports. If the data on the input port changes faster than the master can read, this data may be lost.

     slave address SDA S A6 A5 A4 A3 A2 A1 A0 1 START condition read from port R/W A

     data from port DATA 1 A

     data from port DATA 4

     no acknowledge from master

     1

     P STOP condition

     acknowledge from slave

     acknowledge from master

     DATA 2 data into port th(D) INT tv(Q) td(rst) td(rst)

     002aac121

     DATA 3 tsu(D)

     DATA 4

     A LOW-to-HIGH transition of SDA while SCL is HIGH is dened as the

    STOP condition (P). Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the last acknowledge phase is valid (Output mode). Input data is lost.

     Fig 9. Read input port register

     PCA8574_PCA8574A_2

     NXP B.V. 2007. All rights reserved.

     Product data sheet

     Rev. 02 ?ª 14 May 2007

     8 of 27

     NXP Semiconductors

     PCA8574/74A

     Remote 8-bit I/O expander for I2C-bus with interrupt

     8.4 Power-on reset

     When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA8574/74A in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA8574/74A registers and I2C-bus/SMBus state machine will initialize to their default states. Thereafter VDD must be lowered below 0.2 V to reset the device.

     8.5 Interrupt output (INT)

     The PCA8574/74A provides an open-drain interrupt (INT) which can be fed to a corresponding input of the microcontroller (see Figure 8, Figure 9, and Figure 10). This gives these chips a kind of master function which can initiate an action elsewhere in the system. An interrupt is generated by any rising or falling edge of the port inputs. After time tv(D) the signal INT is valid. The interrupt disappears when data on the port is changed to the original setting or data is read from or written to the device which has generated the interrupt. In the write mode, the interrupt may become deactivated (HIGH) on the rising edge of the write to port pulse. On the falling edge of the write to port pulse the interrupt is denitely deactivated (HIGH). The interrupt is reset in the read mode on the rising edge of the read from port pulse. During the resetting of the interrupt itself, any changes on the I/Os may not generate an interrupt. After the interrupt is reset any change in I/Os will be detected and transmitted as an INT.

     VDD

     device 1

     device 2

     device 8

     PCA8574

     MICROCOMPUTER INT INT

     PCA8574

     PCA8574

     INT

     INT

     002aac682

     Fig 10. Application of multiple PCA8574s with interrupt

     PCA8574_PCA8574A_2

     NXP B.V. 2007. All rights reserved.

     Product data sheet

     Rev. 02 ?ª 14 May 2007

     9 of 27

     NXP Semiconductors

     PCA8574/74A

     Remote 8-bit I/O expander for I2C-bus with interrupt

     9. Characteristics of the I2C-bus

     The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.

     9.1 Bit transfer

     One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 11).

     SDA

     SCL data line stable; data valid change of data allowed

     mba607

     Fig 11. Bit transfer

     9.1.1 START and STOPconditions

     Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is dened as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is dened as the STOP condition (P) (see Figure 12.)

     SDA

     SDA

     SCL S START condition P STOP condition

     SCL

     mba608

     Fig 12. Denition of START and STOP conditions

     9.2 System conguration

     A device generating a message is a ??transmitter??; a device receiving is the ??receiver??. The device that controls the message is the ??master?? and the devices which are controlled by the master are the ??slaves?? (see Figure 13).

     PCA8574_PCA8574A_2

     NXP B.V. 2007. All rights reserved.

     Product data sheet

     Rev. 02 ?ª 14 May 2007

     10 of 27

     NXP Semiconductors

     PCA8574/74A

     Remote 8-bit I/O expander for I2C-bus with interrupt

     SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER I2C-BUS MULTIPLEXER

     SLAVE

     002aaa966

     Fig 13. System conguration

     9.3 Acknowledge

     The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.

     data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition 1 2 8 clock pulse for acknowledgement

     002aaa987

     9

     Fig 14. Acknowledgement on the I2C-bus

     PCA8574_PCA8574A_2

     NXP B.V. 2007. All rights reserved.

     Product data sheet

     Rev. 02 ?ª 14 May 2007

     11 of 27

     NXP Semiconductors

     PCA8574/74A

     Remote 8-bit I/O expander for I2C-bus with interrupt

     10. Application design-in information

     10.1 Bidirectional I/O expander applications

     In the 8-bit I/O expander application shown in Figure 15, P0 and P1 are inputs, and P2 to P7 are outputs. When used in this conguration, during a write, the input (P0 and P1) must be written as HIGH so the external devices fully control the input ports. The desired HIGH or LOW logic levels may be written to the I/Os used as outputs (P2 to P7). During a read, the logic levels of the external devices driving the input ports (P0 and P1) and the previous written logic level to the output ports (P2 to P7) will be read. The GPIO also has an interrupt line (INT) that can be connected to the interrupt logic of the microprocessor. By sending an interrupt signal on this line, the remote I/O informs the microprocessor that there is incoming data or a change of data on its ports without having to communicate via the I2C-bus.

     VDD

     VDD VDD

     CORE PROCESSOR

     SDA SCL INT

     AD0 AD1 AD2

     P0 P1 P2 P3 P4 P5 P6 P7

     temperature sensor battery status control for latch control for switch control for audio control for camera control for MP3

     002aac123

     Fig 15. Bidirectional I/O expander application

     10.2 High current-drive load applications

     The GPIO has a maximum sinking current of 25 mA per bit. In applications requiring additional drive, two port pins in the same octal may be connected together to sink up to 50 mA current. Both bits must then always be turned on or off together. Up to 8 pins (one octal) can be connected together to drive 200 mA.

     VDD

     VDD

     VDD

     CORE PROCESSOR

     SDA SCL INT

     AD0 AD1 AD2

     P0 P1 P2 P3 P4 P5 P6 P7

     LOAD

     002aac124

     Fig 16. High current-drive load application

     PCA8574_PCA8574A_2

     NXP B.V. 2007. All rights reserved.

     Product data sheet

     Rev. 02 ?ª 14 May 2007

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