Circuitizing Requirements Driven by Packaging Designs

By Susan Ray,2014-12-21 21:12
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Circuitizing Requirements Driven by Packaging Designs

Tech Talk, Karl H. Dietz (for February 2001)

Fine Lines in High Yield (Part LXV)

Circuitizing Requirements Driven by Packaging Designs

    I had too much fun with the December Tech Talk column on “Process and Material Adaptations for HDI Requirements”, so I decided to do a follow-up on it. The emphasis will be on the derivation of circuit feature dimensions from HDI packaging designs and a look at photoresist, copper, and circuitizing process requirements.

    Pin count (I/O count) per surface area has been increasing steadily. Pad pitch has been reduced dramatically, requiring smaller circuitry pitch and smaller microvia diameters to fan out the chip I/Os. The chips themselves have not been reduced in size, in fact chips size for high-end applications is going up. Advances in package design from quad flat pack (QFP), to area arrays such as ball grid arrays (BGAs), to chip scale packaging (CSP) and flip chips have reduced the overall footprint for a given I/O count (see Figure 1). This is going hand in hand with a reduction of pitch size. For higher I/O counts, chip size is increasing as shown in Figure 2. A high-end microprocessor with 600-1000 I/Os and a chip I/O pitch of 0.24 mm may require a BGA interposer with eight layers, sequential build-up (SBU) construction, and 30 microns lines and spaces circuitry (see Figure 3).

    Not only circuitry lines and spaces are affected by smaller assembly pitch but also pad sizes, via diameters and land size as shown in Figure 4.

The Impact of Assembly Pitch and I/O Count on Conductor Dimensions.

    Let us look at the PWB pad design for a 0.8 mm pitch CSP assembly (Fig. 5, left section). The 0.5 mm pad diameters on the 0.8 mm grid leave 0.3 mm to accommodate one 100 micron line between pads, plus a 100 micron clearance between the line and the pads. To accommodate two tracks between pads, lines and spaces have to be about 60 microns. With this line and space density one can fan out connections “three deep”, i.e. the first three tiers of pads from an area array. To accomplish the same fan

    out with a 0.5 mm pitch CSP assembly and 0.3 mm PWB pads (see Fig. 5, right section), circuitry lines and spaces have to be approximately 30 microns. To avoid the very fine 30 micron features and to extend the fan out beyond the third tier, designers make use of the third dimension by fanning out pad connections through micro-vias on several layers of circuitry (see Figure 6). The very high pin count example of Figure 3 actually uses a combination of fine circuits ( 30 microns) and multilayer distribution (eight layer interposer) to accomplish the MPU interconnect to the mother board.

Figure 6 shows the classic “dogbone” design used to connect pads to the land of microvias. The off-set

    of micro-vias relative to the pad requires extra space. The planarization of the micro-via surface, e.g., with a metal paste via fill, enables a design by which the pad is placed right on top of the filled via (see Figure 7), allowing much greater pad density.

The Circuitization of 50 ;m Lines and Spaces

    Having looked at assembly pitch and I/O count we can rationalize the need for 50 microns fine circuitry.

    The next question is which circuitizing processes are able to produce such fine features with reasonable yields, and what are the limitations in subtractive and semi-additive processing with regard to allowable copper thicknesses, resist thickness, etch factor and plating thickness uniformity. The study of Reference 1 has highlighted the interrelationships and limitations of these process parameters in a concise way.

    Figure 8 illustrates the etch undercut experienced at the top of the copper line. The undercut has removed about two thirds of the resist/copper anchoring surface. The solid line (“total copper thickness) in Figure 9 shows how the etch factor (k) becomes less favorable as the aspect ratio of the etch channel goes up. As the etch space narrows from 65 ;m to 10;m while the resist thickness remains at 25;m, the

    etch factor shifts from 2.7 to a less favorable 1.6. Therefore, to maintain a given minimum top-of-the-line copper width, the allowable copper thickness for a print & etch process decreases from about 35;m to

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less than 15;m as the pitch goes down from 200;m to 50;m. A panel plating (tent & etch) situation is

    illustrated on the “15;m panel plating”-curve of Figure 9. Given a minimum copper thickness

    requirement in the through-hole of 15;m, and assuming perfect surface copper thickness uniformity and

    throwing power, the base copper cannot be more than 12;m thick for 75;m L/S designs. To circuitize

    50;m L/S patterns with panel plate technology, 5;m base copper is needed, and 30;m L/Ss are

    unattainable. This is the reason why we see a shift to semi-additive pattern plating at 30;m L/S designs

    (see Figure 10). The base copper thickness in this application may be only 3;m.

    Of course, if etch factors and resist thicknesses could be manipulated to a more favorable domain than the scenario of Figure 9, then subtractive circuitizing technology could be extended to finer features. Figure 11 shows the better etch factors attainable with acid vs. alkaline etching. It also illustrates the point that, e.g., in the case of 50;m photoresist spaces, a 2;m thick resist yields a more favorable etch

    factor than the 25;m thick resist. This fact is one of the drivers behind the trend towards thinner dry film resist developments and process improvements that enable the performance of such thinner resists, e.g., higher lamination pressure or wet lamination technology.


    1. Allowable Copper Thickness for Fine-Pitch Patterns Formed by a Subtractive Method, Takuya Yamamoto, Takashi Kataoka and John Andresakis, CircuiTree Magazine, June 2000, Volume 13, No. 6, pg. 112 (see also Proceedings of the Technical Conference, S-07-3, IPC Printed Circuit Expo, San Diego, CA, April 4-6, 2000)


    Permission to use illustrations provided by my colleague Toru Takahashi and by T. Yamamoto, T. Kataoka, and J. Andresakis, (Mitsui M. & M., Oak-Mitsui) is gratefully acknowledged. KHD-2010-12-21 2

    Package (ASIC, Memory, Logic) Style Evolution Molding IC chip Lead QFDframe