Definition of Jitter Values

By William Lewis,2014-08-09 14:29
16 views 0
Definition of Jitter Values

Definition of Jitter Values

    The maximum jitter values in terms of percentage of Unit Interval (UI = 400 ps for 2.5 GT/s) are specified for the system board and the add-in card. The jitter associated with the riser card and associated proprietary connector will be part of the system board jitter budget. The jitter values are defined with respect to 100 Ω differential termination, realized

    as two 50 Ω resistances. These resistances are referenced to ground at the interface (see Figure 4-5).

    The total system jitter budget is derived with the assumption of a minimum Rj for each of the four budget items. This minimum Rj component is used to determine the overall system budget. Theprobability distribution of the Rj component is at the Bit Error Rate (BER) indicated and is Gaussian. For any jitter distribution the total Tj must always be met at the BER. The Rj of the components are independent and convolve as the root sum square. Tradeoffs of Rj and Dj are allowed, provided the total Tj is always met.

REFCLK Phase Jitter Specification For 2.5 GT/s

    The phase jitter of the reference clock is to be measured using the following clock recovery Function

    The maximum allowed magnitude of the peak-peak reference clock jitter is given in Table 2-2. Multiple methods can be used to measure the maximum allowed peak-peak phase jitter value. Real time sampling scopes must use a sampling rate of 20 giga-samples per second or better and take enough data to guarantee the proper bit error rate (BER). Reference clock measurements for cards should be taken with a differential, high-impedance probe using the circuit of Figure 2-9 at the load capacitors CL. Measurements for devices on the same board should be made using a differential, high-impedance probe as close to the REFCLK+ and REFCLK- input pins as possible.

Eye Diagrams at the Add-in Card Interface

    The eye diagrams defined in this section represent the compliance eye diagrams that must be met for both the add-in card and a system board interfacing with such an add-in card. The specific measurement requirements (probe test points, calibrated system board specifics, etc.) for compliance of physical components are to be specified in the PHY Electrical Test .

Add-in Card Transmitter Path Compliance Eye Diagram at 2.5 GT/s

Add-in Card Minimum Receiver Path Sensitivity Requirements at 2.5 GT/s

System Board Transmitter Path Compliance Eye Diagram at 2.5 GT/s

System Board Minimum Receiver Path Sensitivity Requirements at 2.5 GT/s

Report this document

For any questions or suggestions please email