Definition of Jitter Values
The maximum jitter values in terms of percentage of Unit Interval (UI = 400 ps for 2.5 GT/s) are specified for the system board and the add-in card. The jitter associated with the riser card and associated proprietary connector will be part of the system board jitter budget. The jitter values are defined with respect to 100 Ω differential termination, realized
as two 50 Ω resistances. These resistances are referenced to ground at the interface (see Figure 4-5).
The total system jitter budget is derived with the assumption of a minimum Rj for each of the four budget items. This minimum Rj component is used to determine the overall system budget. Theprobability distribution of the Rj component is at the Bit Error Rate (BER) indicated and is Gaussian. For any jitter distribution the total Tj must always be met at the BER. The Rj of the components are independent and convolve as the root sum square. Tradeoffs of Rj and Dj are allowed, provided the total Tj is always met.
REFCLK Phase Jitter Specification For 2.5 GT/s
The phase jitter of the reference clock is to be measured using the following clock recovery Function