UnixLinux Cheat Sheet Development Tools 2

By Bobby Sims,2014-08-11 01:24
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UnixLinux Cheat Sheet Development Tools 2

    Unix/Linux Cheat Sheet Development Tools 2

make- a tool to manage the building of executable files. A makefile is required that

    specifies dependencies and rules.

A makefile specifies how an application will be built.

    A dependency consists of a target to be built (usually an executable program or an object file) and the dependent files that are needed to build it.

A rule specifies how to build the target using the dependent files.

If a target’s dependent files have been changed more recently than the target it must be

    rebuilt using the rules specified in the makefile. Each file has a “last modified time” attribute that tells when the file has changed last. These dates are used by make.


     -f filename used when your makefile has a name other than “makefile” or


    -k tells the make command to keep going instead of stopping at the first error in

     the build process. This will tell you which source files fail to compile.

    -n tells make to printout what it would have done without actually doing it.

    Your makefile must use tabs and not spaces on the lines with rules. Also, the lines of a makefile must not end with a space.

    make will attempt to make the first dependency in the file. It is standard practice to include a dependency called all with the dependent file being the executable (see the

    makefile on the back of this page).

One can include a rule called clean with no dependent files. When make is called with

    the name of the dependency only that rule will be invoked.


     -rm *.o

    Macros in makefiles allow the names of the development tools to be declared once in the file. If the name of a tool ever changes we only need to change it once in the makefile.

     CC = g++

To use the macro in the file use a $ and a set of parenthesis

     $(CC) o my app *.o

    To invoke the make program from the command line

     &> make

This will cause make to look for a file called makefile or Makefile in the current directory

    and start building the application using the first dependency.

     &> make clean

    This will cause the dependency clean to be executed to remove object files

    This is a makefile to create an application called myapp

    all: myapp

    # name of the compiler

    CC = g++

    # path of include files

    INCLUDE = ../header

    # compiler flags

    CFLAGS = -g Wall ansi

    myapp: main.o file2.o file3.o

     $(CC) o myapp main.o file2.o file3.o

    main.o: main.cpp a.h

     $(CC) I$(INCLUDE) $(CFLAGS) c main.cpp

    file2.o: file2.cpp a.h b.h

     $(CC) I$(INCLUDE) $(CFLAGS) c file2.cpp

    file3.o: file3.cpp b.h c.h

     $(CC) I$(INCLUDE) $(CFLAGS) c file3.cpp


     -rm main.o file2.o file3.o

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