TXT

381_e MOS pass-transistor network

By Harold Warren,2014-10-14 16:39
11 views 0
381_e MOS pass-transistor network

     ??ÎÄÓÉjcl2jzcon5??Ï×

    pdfÎĵµ?ÉÄÜÔÚWAP?Ëä?ÀÀÌåÑé???Ñ????ÒéÄúÓÅÏÈÑ?ÔñTXT???òÏÂÔØÔ?ÎÄ?þµ????ú?é????

     IEICE TRANS. ELECTRON., VOL.E82?CC, NO.9 SEPTEMBER 1999

     1662

     PAPER

     Special Issue on Integrated Electronics and New System Paradigms

     Multiple-Valued Logic-in-Memory VLSI Architecture Based on Floating-Gate-MOS Pass-Transistor Logic

     Takahiro HANYU?a) and Michitaka KAMEYAMA? , Members

     ???? D?? 1 ??1? ????Y ?Á???? ???? ? ? ?? ?? ?? ?Á? ?? ? - ?Á ?º?? ? ????D?? Y? ?????1?? D?? ??DD ?

     1. Introduction

     SUMMARY A new logic-in-memory VLSI architecture based on multiple-valued ?oating-gate-MOS pass-transistor logic is proposed to solve the communication bottleneck between memory and logic modules. Multiple-valued stored data are represented by the threshold voltage of a ?oating-gate MOS transistor, so that a single ?oating-gate MOS transistor is e?ectively employed to merge multiple-valued threshold-literal and pass-switch functions. As an application, a four-valued logicin-memory VLSI for high-speed pattern recognition is also presented. The proposed VLSI detects a stored reference word with the minimum Manhattan distance between a 16-bit input word and 16-bit stored reference words. The e?ective chip area, the switching delay and the power dissipation of a new four-valued full adder, which is a key component of the proposed logic-inmemory VLSI, are reduced to about 33 percent, 67 percent and 24 percent, respectively, in comparison with those of the corresponding binary CMOS implementation under a 0.5-?Ìm ?ash EEPROM technology. key words: ? ?Á?Á1?? ???Á ?Á???? ?? ????? ? -?? ? ?? 1 ? ??? ?? ???Á ?Á1

     ??1

     Communication bottleneck between memory and logic modules is one of the most serious problems in recent deep submicron VLSI systems, especially in the multimedia VLSI systems on a single chip [1]. A logic-inmemory structure, in which storage functions are distributed over a logic-circuit plane, is a key technology to solve the above problem [2]. When a small amount of storage is included in each cell of a logic-in-memory VLSI array, its VLSI array may be regarded either as a logically enhanced memory array, or as a logic array whose elementary gates and connections can be programmed to realize a desired logical behavior. However, the VLSI array is more complex to build and has lower storage density than a normal memory because of the overhead involved in the storage and logic elements. On the other hand,

    a ?oating-gate MOS transistor is generally used as a memory cell device of ?ash EEPROMs [3]. Since a ?oating-gate MOS transistor can be utilized not only as a memory element but also as a switching one, the circuit design using ?oatinggate MOS transistors has a potential advantage to realManuscript received January 25, 1999. Manuscript revised March 29, 1999. ? The authors are with the Department of Computer and Mathematical Sciences, Graduate School of Information Sciences, Tohoku University, Sendai-shi, 980-8579 Japan. a) E-mail:

    hanyu@kameyama.ecei.tohoku.ac.jp

     ize high-performance VLSI systems with less communication bottleneck between storage and logic elements. However, very few VLSI circuits using such ?oatinggate MOS transistors are designed and implemented as hardware accelerator in a special-purpose VLSI [4]?C[6]. In this paper, a new logic-in-memory VLSI based on pass-transistor logic [7], [8] and ?oating-gate MOS transistors, called ???oating-gate-MOS pass-transistor logic,?? is proposed to merge storage and switching functions in a multiple-valued-input and binary-output combinational logic circuit. The proposed logic-inmemory VLSI is useful for the realization of parallel arithmetic and logic circuits. Four basic operations such as AND (serial connection of pass transistors), OR (parallel connection of pass transistors), a threshold literal and logic-value conversion are used to represent arbitrary switching functions. Multiple-valued stored data are represented by the threshold voltage of a ?oating-gate MOS transistor [9], so that both multiplevalued threshold-literal and pass-switch functions can be merged by using a single ?oating-gate MOS transistor. Consequently, a compact pass-transistor network can be designed by using ?oating-gate MOS transistors. As an e?cient application, a logic-in-memory VLSI based on four-valued ?oating-gate-MOS pass-transistor logic is also presented to detect a stored reference word with the minimum Manhattan distance [10] between a 16-bit input word and 16-bit stored reference words. The basic components of the proposed logic-in-memory VLSI are mainly a four-valued adder and a winner-takeall (WTA) circuit [11]. The former can be designed compactly by using ?oating-gate MOS pass-transistor network. Moreover, the use of precharge-evaluate logic in a ?oating-gate-MOS pass-transistor network makes it possible to reduce the power dissipation as well as to improve the switching speed with less area penalty. Since highly parallel logic operations and storage functions are merged in the pass-transistor network, the number of transistors is greatly reduced in the embedded four-valued adder. In fact, the e?ective chip area, the switching delay and the power dissipation of the four-valued full adder in the proposed logic-in-memory VLSI are reduced to about 33 percent, 67 percent and 24 percent, respectively, in comparison with those of the corresponding

    binary CMOS implementation under a 0.5-?Ìm CMOS technology.

     HANYU and KAMEYAMA: MULTIPLE-VALUED LOGIC-IN-MEMORY VLSI

     1663

     Fig. 1

     Combinational logic-circuit model.

     2.

     General Structure of a Floating-Gate-MOS Pass-Transistor Network

     Figure 1 shows a general structure of a combinational logic circuit. It has two kinds of R-valued inputs, S (n-digit external inputs) and B (n-digit internal (stored constant) inputs), and binary outputs, Z (mbit external outputs), where sj = {0, 1, ?? ?? ?? , R ? 1}, bj = {0, 1, ?? ?? ?? , R ? 1} (1 ?Ü j ?Ü n) and zi = {0, 1} (1 ?Ü i ?Ü m). In the following description, we discuss about this type of a combinational logic circuit model. 2.1 Basic Components in a Four-Valued-Input BinaryOutput Pass-Transistor Network Figure 2(a) shows a general structure of a four-valuedinput binary-output pass-transistor network [8]. Four kinds of operations, AND, OR, a threshold literal and logic-value conversion (LVC), are basic building blocks in the above pass-transistor network where AND and OR operations are performed by using series and parallel connections of pass transistors, respectively. LVC is an input-value converter in which an Rvalued input value is converted into an arbitrary Rvalued output value. LVC is a one-variable function which is de?ned by f =< p0 , p1 , ?? ?? ?? , pn?1 > as ? if s = 0, ? p0 ? ? ? p1 if s = 1, (1) f (s) = . . . . ? . . ? ? ? pR?1 if s = R ? 1 where pi ?Ê {?1, 0, ?? ?? ?? , R?2, R?1}. Only a four-valued LVC, f =< 3, 2, 1, 0 >, is used in Fig. 2(a). A threshold literal is a four-valued-input binaryoutput function which is de?ned as T (x, y) = Ty (x) = 1 if x > y, 0 otherwise (2)

     Fig. 2 Pass-transistor network with four-valued inputs and a binary output.

     2.2 Floating-Gate-MOS Pass-Transistor Network A ?oating-gate MOS transistor is one of the key devices to realize a logic-in-memory VLSI circuit, because it can be used as a multiple-valued logic element as well as a one-digit multiple-valued storage element. Figure 3(a) shows a pass gate using a single ?oating-gate MOS transistor which merges a threshold literal into a pass-switch operation. The control-gate voltage Vc and the threshold Voltage Vt in a ?oatinggate MOS transistor correspond to an external input x and a stored input y, respectively, whose relationships are given in R-valued logic as Vc = Vdd ?? x, R?1 Vdd Vt = ?? (y + 0.5) R?1 (3) (4)

     where x ?Ê {0, 1, ?? ?? ?? , R ? 2, R ? 1}, y ?Ê {?1, 0, ?? ?? ?? , R ? 2, R ? 1}. In the speci?cation given in Fig. 2(b), four threshold literals, Ty1 (x),Ty2 (x),Ty3 (x) and Ty4 (x) are programmed as shown in Fig. 2(c) where a four-valued stored input b is ?xed at a logic value

    ??2.?? In this way, an arbitrary combinational logic circuit with a fourvalued input and a binary output is designed by programming the threshold literals in Fig. 2(a).

     where Vdd is a power supply voltage. In four-valued

     IEICE TRANS. ELECTRON., VOL.E82?CC, NO.9 SEPTEMBER 1999

     1664

     Fig. 3 Table 1

     Floating-gate-MOS pass-transistor network.

     Relationship between logic values and voltage levels.

     Fig. 4 Logic-in-memory VLSI for the nearest pattern matching.

     logic with Vdd = 5 V, Vc and Vt are given by Eqs. (3) and (4), respectively, as shown in Table 1. Using this ?oating-gate-MOS pass transistors, the combinational logic circuit shown in Fig. 2(a) can be simply realized as shown in Fig. 3(b). 3. Design of a Logic-in-Memory VLSI for the Nearest Pattern Matching

     where aj and bij (1 ?Ü j ?Ü n) indicate the j-th digit of A and Bi , respectively, and where aj , bij ?Ê {0, 1, 2, 3}. The Manhattan distance Di between A and Bi is de?ned by the absolute value of the di?erence which is described as Di =| A ? Bi | . (7)

     As an e?cient application of the multiple-valued ?oating-gate-MOS pass-transistor network, a highly parallel and compact logic-in-memory VLSI to perform the nearest pattern-matching operations between a four-valued n-digit input word and a stored word is designed. The similarity between two words is calculated by the Manhattan distance. 3.1 Hardware Algorithm Figure 4 shows a block diagram of the logic-in-memory VLSI for the nearest pattern matching. A four-valued input n-digit word A and the i-th stored word Bi (1 ?Ü i ?Ü m) are expressed as

     n

     A=

     j=1 n

     4n?j ?? aj ,

     (5)

     In Eq. (7), there are two kinds of basic operations, subtraction (A ? Bi ) and its absolute-value computation (ABS). Since the subtraction and its ABS for an input A are performed in parallel by every word circuit, each word circuit must be designed as compactly as possible. Hence, we choose a four-valued ripple-carry addition scheme to make the adder compact. Table 2 shows the truth tables of a four-valued full adder, where the i-th sum is described by two-bit binary codes as (s2i , s2i?1 ), and where the i-th carry is described by a one-bit code as ci . Since the sums (s2i , s2i?1 ) are represented by the two??s complement expression, the output of ABS is determined by the carry cn from the most-signi?cant digit. Namely, if the di?erence (s2i , s2i?1 ) is

    negative, then cn becomes ??1.?? Otherwise, cn = 0. As a result, the Manhattan distance Di between A and Bi shown in Eq. (7) is rewritten as Di = (sn sn?1 ?? ?? ?? s2 s1 ) (sn sn?1 ?? ?? ?? s2 s1 ) if cn = 0, if cn = 1. (8)

     Bi =

     j=1

     4n?j ?? bij

     (6)

     where si is the complement of si . The nearest pattern

     HANYU and KAMEYAMA: MULTIPLE-VALUED LOGIC-IN-MEMORY VLSI

     1665 Table 2 Truth table of four-valued addition.

     matching can be performed according to Eq. (8) in the i-th word, where the i-th output Oi from the word circuit is described as ? if Di is the minimum of all the ? 1 other Dk (k = i) , Oi = (9) ? 0 otherwise. 3.2 Circuit Realization Figure 5(a) shows a circuit diagram of a four-valued full adder based on ?oating-gate-MOS pass-transistor logic. The peripheral circuits to distribute four-valued input voltages in the logic-in-memory plane and to program one of ?ve-valued threshold voltages in each ?oatinggate MOS transistor can be designed by using the almost same peripheral ones in a multilevel NAND ?ash memory [12]. The Block1 in Fig. 5 is the circuit for s2i?1 in case of ci?1 , that is designed by the seriesparallel connection of three ?oating-gate MOS transistors because three threshold literals are required in the realization of s2i?1 . Similarly, the number of ?oatinggate MOS transistors in the other circuit blocks is also determined by the number of the required threshold literals. As a result, a four-valued full adder can be designed by 34 transistors, in which four-valued storage functions are merged as well as an addition with four-valued inputs and binary outputs. Figure 5(b) shows input and output waveforms of the proposed four-valued full adder by using HSPICE simulation. The use of precharge-evaluate logic makes it possible to reduce the switching delay of the proposed full adder with less area penalty. Moreover, all the outputs of the proposed pass-transistor network become compatible with standard binary CMOS gates because the binary inverters are used as their output bu?ers. Figure 6 shows a circuit and a layout of the basic cell for the nearest pattern-matching operations. It consists of the proposed four-valued full adder with a two-bit storage capability, two ABS circuits, a two-tofour encoder and a four-valued WTA circuit. The two-

     (a) Circuit diagram

     (b) HSPICE simulation Fig. 5 Four-valued full adder.

     bit outputs from a four-valued full adder are modi?ed in the corresponding ABS circuits, respectively, where the absolute values of (s2i , s2i?1 ) are controlled by the carry c8 from the most-signi?cant

    digit as shown in Eq. (8). Since the WTA circuit is designed by the current-mode logic [11], two-bit voltage-mode outputs from two ABS circuits are converted to a four-valued current-mode input in the WTA circuit by a two-tofour encoder. Figure 6(c) shows input and output waveforms of a basic cell by using HSPICE simulation, where the equivalent circuit of a ?oating-gate MOS transistor

     IEICE TRANS. ELECTRON., VOL.E82?CC, NO.9 SEPTEMBER 1999

     1666

     Fig. 6

     Basic-cell structure of the logic-in-memory VLSI.

     used in the HSPICE simulation is composed of a standard nMOS transistor, a capacitor and a resistor as shown in Fig. 6(d). When a one-digit di?erence S is 3 (the maximum value), the output of the WTA becomes 0 in the simulation. In case of S = 2, the switching delay between an ABS and a WTA is maximum. The reason is that another WTA input S on the same row is set to 2 in the simulation. Since each component is designed simply in the basic cell, its critical path becomes short enough, which results in a short switching delay in the basic cell. Figure 7 shows a layout of the logic-in-memory VLSI for the nearest pattern matching between two words. The chip area is 11.2 ?Á 16.0 mm2 under a standard 0.5-?Ìm ?ash EEPROM technology. This chip includes 32,768 16-bit words whose stored data are programmable by changing the threshold voltage of ?oating-gate MOS transistors.

     3.3 Evaluation Since the basic components except the four-valued full adder in a basic cell are simple enough, it is very important to design a high-performance full adder. To demonstrate the advantage of the proposed ?oatinggate-MOS pass-transistor network, we evaluate the performance of the proposed four-valued full adder with a two-bit storage capability in comparison with that of three di?erent two-bit adders. As shown in Fig. 8(a), a binary full adder with a one-bit storage capability is desinged by the combination of standard binary CMOS gates. In addition to the combinational circuit for three-bit addition, six transistors are required to store one bit using an Static RAM-like cell. Figure 8(b) shows another binary full adder, called ??Manchester Carry Adder?? using a pass-transistor network [13], where a one-bit storage element based on an SRAM-like cell is also required in the full adder. The total number of transistors in the Manchester Carry

     HANYU and KAMEYAMA: MULTIPLE-VALUED LOGIC-IN-MEMORY VLSI

     1667 Table 3 Comparison of four-valued full adders.

     Fig. 7

     Overall structure of the logic-in-memory VLSI.

     realize high-speed and low-power pass-transistor networks such as the proposed four-valued full adder and the Manchester Carry Adder. In the proposed fourvalued full adder, a four-valued stored data bji

    is preliminarily programmed as the threshold voltages of the corresponding ?oating-gate MOS transistors. Since a ?oating-gate MOS transistor is used as a storage element for the stored data, no additional circuits for storage are required in the proposed hardware, which results in reduced transistor counts. In contrast, when storage elements and logic functions are not merged in the same circuits, the total transistor counts become larger. Using the ?oating-gate-MOS pass-transistor network, the performance of the proposed logic-in-memory VLSI is superior to those of any other ones in terms of the chip area and the power dissipation under the same switching speed. In fact, the chip area, the switching delay and the power dissipation of the proposed full adder are reduced to about 33 percent, 67 percent and 24 percent, respectively, in comparison with those of the corresponding binary CMOS implementation. 4. Conclusion

     (a) Binary CMOS implementation

     (b) Manchester carry adder Fig. 8 Binary full adders.

     Adder with a two-bit storage capability is less than half in comparison with that of the binary CMOS implementation shown in Fig. 8(a). Table 3 summarizes the comparison of four-valued full adders under a 0.5-?Ìm ?ash EEPROM technology. The precharge-evaluate logic design [14] is used to

     A new pass-transistor network using ?oating-gate MOS transistors has been proposed to design a highperformance combinational logic circuit with fourvalued inputs and binary outputs. The design method of the multiple-valued pass-transistor network is easily utilized in a four-valued logic-in-memory VLSI. Its performance is much superior to that of an ordinary non-logic-in-memory implementation in terms of area and power dissipation under the same switching speed. The design concept to merge storage and switching functions and to use ?oating-gate MOS transistors as a key device makes it possible to realize such a highperformance logic-in-memory VLSI architecture. The

    proposed ?oating-gate MOS pass-transistor network is suitable for any combinational logic-circuit design with multiple-valued external and stored inputs and binary output. As a future prospect of the proposed multiplevalued logic-in-memory VLSI, it would be important to

     IEICE TRANS. ELECTRON., VOL.E82?CC, NO.9 SEPTEMBER 1999

     1668

     design its peripheral circuits such as a charge-pumping circuit for a single supply voltage and to evaluate these performance.

     References [1] J. Borel, ??Technologies for multimedia systems on a chip,?? Digest of Technical Papers, IEEE International SolidStateCircuits Conference, TA1.1, pp.18?C21, Feb. 1997. [2] W.H. Kautz, ??Cellular logic-in-memory arrays,?? IEEE Trans. Comput., vol.C-18, no.8, pp.719?C727, Aug. 1969. [3] C. Hu, Nonvolatile

    Semiconductor Memories Technologies, Design and Applications, IEEE Press, 1991. [4] T. Hanyu, N. Kanagawa, and M. Kameyama, ??Design of a one-transistor-cell multiple-valued CAM,?? IEEE J. SolidState Circuits, vol.SC-31, no.11, pp.1669?C1674, Nov. 1996. [5] T. Hanyu, K. Teranishi, and M. Kameyama, ??Design and evaluation of a digit-parallel multiple-valued contentaddressable memory?? IEICE Trans. vol.J81-D-I, no.2, pp.151?C156, Feb. 1998. [6] T. Hanyu, K. Teranishi, and M. Kameyama, ??Multiplevalued ?oating-gate-MOS pass logic and its application to logic-in-memory VLSI,?? IEEE International Symposium on Multiple-Valued Logic, pp.270?C275, May 1998. [7] D. Radhakrishnan, S.R. Whitaker, and G.K. Maki, ??Formal design procedures for pass transistor switching circuits?? IEEE J. Solid-State Circuits, vol.SC-20, no.2,pp.531?C536, April 1985. [8] A. Parameswar, H. Hara, and T. Sakurai, ??A high speed, low power, swing restored pass-transistor logic based multiply and accumulate circuit for multimedia applications,?? Proc. IEEE 1994 Custom Integrated Circuits Conf., pp.278?C281, May 1994. [9] T. Higuchi and M. Kameyama, Multiple-Valued Digital Processing System, Shokodo Co. Ltd., Tokyo, 1989. [10] A. Gersho and R.M. Gray, Vector Quantization and Signal Compression, Kluwer Academic Publishers, Boston, 1992. [11] J. Lazzaro, S. Ryckebusch, M.A. Mahowald, and C.A. Mead, ??Winner-take-all network of O(N) complexity,?? in Advances in Neural Information Processing Systems 1 ed. D. Touretzky, Morgan Kaufmann, pp.703?C711, San Mateo, CA, 1989. [12] T.S. Jung, Y.J. Choi, K.D. Suh, B.H. Suh, J.K. Kim, Y.H. Lim, Y.N. Koh, J.W. Park, K.J. Lee, J.H. Park, K.T. Park, J.R. Kim, J.H. Yi, and H.K. Lim, ??A 117-mm2 3.3-V only 128-Mb multilevel NAND ?ash memory for mass storage applications?? IEEE J. Solid-State Circuits, vol.SC31, no.11, pp.1575?C1582, Nov. 1996. [13] T. Kilburn, D.B.G. Edwards, and D. Aspinall, ??Parallel addition in digital computers: A new-fast carry circuit,?? Proc. IEE, vol.106, part B, no.29, pp.464?C466, Sept. 1959. [14] R.L. Geiger, P.E. Allen, and N.R. Strader, VLSI: Design Techniques for Analog and Digital Circuits, McGraw-Hill, 1990.

     Takahiro Hanyu received the B.E., M.E. and D.E. degrees in Electronic Engineering from Tohoku University, Sendai, Japan, in 1984, 1986 and 1989, respectively. He is currently an Associate Professor in the Graduate School of Information Sciences, Tohoku University. His general research interests include multiple-valued logic and its application to intelligent integrated systems. He received the Outstanding Paper Awards at the 1985 and 1987 IEEE International Symposiums on MultipleValued Logic (with M. Kameyama et al.) and the Niwa Memorial Award in 1988. Dr. Hanyu is a member of the IEEE.

     Michitaka Kameyama received the B.E., M.E. and D.E. degrees in Electronic Engineering from Tohoku University, Sendai, Japan, in 1973,

    1975, and 1978, respectively. He is currently a Professor in the Graduate School of Information Sciences, Tohoku University. His general research interests include intelligent integrated systems for real-world application and robotics, VLSIprocessors for highly-safe intelligent systems, and multiple-valued VLSI systems. Dr. Kameyama received the Outstanding Paper Awards at the 1984, 1985, 1987, and 1989 IEEE International Symposiums on Multiple-Valued Logic, the Technically Excellent Award from the Society of Instrument and Control Engineers of Japan in 1986, the Outstanding Transactions Paper Award from the IEICE in 1989, and the Technically Excellent Award from the Robotics Society of Japan in 1990. Dr. Kameyama is a Fellow of the IEEE.

??TXTÓÉ??ÎÄ?â????ÏÂÔØ:http://www.mozhua.net/wenkubao

Report this document

For any questions or suggestions please email
cust-service@docsford.com