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SynTest Products

By Ruby Johnson,2014-09-27 12:09
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SynTest Products

    SynTest Products

DFT-PRO Plus

    VirtualScan

    TurboBIST-Logic

    TurboBIST-Memory

    TurboFault

    TurboCheck

    TurboScan

    TurboBSD

    TurboDFT

DFT- PRO Plus ? - A Comprehensive Package of DFT Tools view data sheet

    DFT-PRO Plus ? offers an integrated DFT solution covering scan synthesis and ATPG, memory Built-In Self-Test (BIST) synthesis and boundaryscan (BSD) synthesis. The corresponding tools generate RTL blocks that fit seamlessly into an existing synthesis flow. This gives the user the freedom to choose any commercially available logic and scan synthesis tools from vendors like Cadence, Incentia, Magma, Mentor, Synopsys or Synplicity and enables a one-pass RTL to GDSII synthesis flow. It also eases overall design floor planning.

VirtualScan? - Tool Suite for Virtual Scan Synthesis and ATPG view data sheet

    VirtualScan? is SynTest's solution to combat this increase in test data volume and test cycle volume. With VirtualScan? an extremely large number of short scan chains within the SOC can be virtually accessed from outside the chip with a limited number of pins assigned as scan pins. Inside the chip,SynTest's new patent-pending circuitry is used to broadcast each external scan-input chain to a user-selectable number of internal scan chains and at the other end, compact them into the original number of external scan chains. An evaluation on a 2-million gate design using VirtualScan? showed a 22x reduction in test time. Further, the static and dynamic

    compaction capabilities of SynTest's powerful ATPG tool help reduce pattern sizes, leading to overall reduction in test costs.

TurboBIST? - Built-in Self-Test view TurboBIST-Logic data sheet view

    TurboBIST-Memory data sheet

    TurboBIST? family of products from SynTest Technologies, Inc. includes tools for logic (TurboBIST? - Logic) and memory (TurboBIST? - Memory) (SRAM, ROM, DRAM and CAM)

    built-in self-test. These tools synthesize the BIST logic surrounding functional logic and memory blocks, including IP cores from third party suppliers, and automatically generate the test patterns needed to provide very high fault coverage testing of complete complex system-on-silicon chips.

TurboFault? - Fault Simulation view data sheet

    TurboFault? combines high performance, versatility and accuracy. It is highly competitive with hardware accelerators for classical test fault grading. It supports synchronous and asynchronous designs at the gate level, including tri-state gates, latches, flip-flops, single and multi-port RAMs, complex bus resolution functions, and User Defined Primitives (UDPs). TurboFault reads Verilog gate-level netlists, and will also read Standard Delay Format (SDF) timing files.

TurboCheck? - Testability Analysis view data sheet

    TurboCheck? is a Testability Analyzer and Test Assistant for both RTL (Register-Transfer-Level) and gate-level digital designs. TurboCheck analyzes the testability of sequential circuits and assists the designer in selecting test solutions that are most likely to improve the circuit's final fault coverage. TurboCheck operates on non-scan, partial-scan, or full-scan circuits. Because it is a static tool operating on the topology of the circuit, no vectors are needed for the analysis.

    TurboScan - Scan Synthesis and ATPG veiw data sheet

    TurboScan? is an advanced full-scan and partial-scan test suite. It includes a Scan Synthesizer and an Automatic Test Pattern Generator (ATPG). TurboScan automatically repairs testability violations to make your design highly testable. The ATPG engine uses advanced search and compaction algorithms to achieve very high fault coverage and produce up to 50% smaller test pattern size. TurboScan is designed to reduce product defect level and save test costs.

TurboBSD? - Boundary Scan view data sheet

    TurboBSD? is SynTest high-performance Boundary Scan Designer. It is 100% compliant to the IEEE 1149.1 Boundary Scan Standard. TurboBSD performs Boundary Scan logic synthesis, creates BSDL (Boundary Scan Description Language) file, and generates Boundary Scan test patterns. All these tasks are fully automated by the tool, making boundary scan design a straightforward process.

TurboDFT? - Integration Tool Suite view data sheet

    TurboDFT? contains a suite of very useful and powerful DFT integration tools. TurboDFT allows users to automatically integrate and stitch DFT cores, whether they are created using DFT tools from SynTest or other vendors. Rtlmsdb scripts and commands are provided for allowing users to automatically stitch DFT cores with or without boundary-scan control. Thus, TurboDFT brings "Ease of integration" benefit and eliminates the tedious, error-prone manual stitching process.

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