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template based soc design verification

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template based soc design verification, using AN INDUSTRY SOC as an example

     SOC Design Verification Whitepaper

    TEMPLATE BASED SOC DESIGN VERIFICATION,

    USING AN INDUSTRY SOC AS AN EXAMPLE

    PREPARED BY

    ISSAC LIAN

    JULY 19, 2005

    ?Copyright 2004 Be One Lab Inc (All Rights Reserved) 1

     SOC Design Verification Whitepaper

1. Review History

    Revision Date Person Comment

    1.0 July 19, 2005 Issac Lian Initial creation

    ?Copyright 2004 Be One Lab Inc (All Rights Reserved) 2

     SOC Design Verification Whitepaper

    1. Review History ....................................................................................................................................................... 2 2. Abstract ................................................................................................................................................................... 4 3. Introduction ............................................................................................................................................................ 4 4. What to test ............................................................................................................................................................. 4

    4.1. Atomic features by the method of Connectivity Matrix ............................................................................. 4

    4.1.1. What needs to be tested................................................................................................................... 4

    4.1.2. Feature Coverage Matrix ................................................................................................................ 5

    4.2. Inter-Atomic features by the method of Interactivity Matrix ...................................................................... 6

    4.2.1. What needs to be tested................................................................................................................... 6

    4.2.2. Feature Coverage Matrix ................................................................................................................ 7

    4.3. Features by the method of Shared Resource ............................................................................................... 7

    4.3.1. Atomic features on Memory ........................................................................................................... 7

    4.3.2. Inter-Atomic features on Memory .................................................................................................. 8

    4.3.3. Asynchronous timing feature by the method of fault model from Virgo project at DDR2 interface

     9

    4.3.4. Features on Memory Map Access ................................................................................................... 9

    4.3.5. Features on Register Map Access ................................................................................................. 10

    4.4. Features by the method of Bus Hardening ................................................................................................ 10

    4.4.1. What needs to be tested................................................................................................................. 10

    4.4.2. Feature Coverage Matrix .............................................................................................................. 10

    4.5. Features by the method of Configuration Matrix...................................................................................... 11

    4.5.1. What needs to be tested................................................................................................................. 11

    4.5.2. Feature Coverage Matrix .............................................................................................................. 11

    4.6. Features by the method of SW/HW Co-verification Matrix ..................................................................... 11

    4.6.1. What needs to be tested................................................................................................................. 11

    4.6.2. Feature Coverage Matrix .............................................................................................................. 11

    4.7. Features of Reset....................................................................................................................................... 12

    4.7.1. What needs to be tested................................................................................................................. 12

    4.7.2. Feature Coverage Matrix .............................................................................................................. 12

    4.8. Features Test and Debug ........................................................................................................................... 12

    4.8.1. What needs to be tested................................................................................................................. 12

    4.8.2. Feature Coverage Matrix .............................................................................................................. 12

    4.9. Features of Gate Level Testing ................................................................................................................. 13

    4.9.1. What needs to be tested................................................................................................................. 13

    4.9.2. Feature Coverage Matrix .............................................................................................................. 13

    5. How to test ............................................................................................................................................................ 13

    5.1. Testbench environment overview ............................................................................................................. 13

    5.2. Required testbench components ............................................................................................................... 15

    5.3. How is test case written and run ............................................................................................................... 15

    5.4. Required coverage components ................................................................................................................ 15

    6. Coverage checklist Feedback of “what is indeed covered by the testcases.” .................................................... 16 7. Conclusion, limitation, and future work ............................................................................................................... 18 ?Copyright 2004 Be One Lab Inc (All Rights Reserved) 3

     SOC Design Verification Whitepaper

2. Abstract

    This reports presents a template approach towards SOC design verification. This approach offers automation on the two most important issues of any SOC/ASIC design verification: what to test and how to test.

    In addition, the concept of coverage is introduced. Coverage is defined tightly with features and implementations, so it can efficiently serve as a feedback to test case creation and test bench development. Defining a template based, and complete coverage checklist early in the project flow also enables the team to better estimate the efforts required.

3. Introduction

    SOC design verification is a challenging engineering process. Many risk factors exist and they can be partitioned into two categories: what and how. The what factor refers to what to test and decides the functional

    correctness of the SOC in terms of coverage. The how factor refers to how to test and decides the amount of

    engineering efforts required to achieve the coverage.

Using Celestialsemi’s Orion SOC as an example, this report provides templates for:

    ; What to test

    ; How to test

    ; Coverage checklist Feedback of what is indeed covered by the testcases.

Finally, we present our conclusion, limitation, future work items.

    4. What to test

    4.1. Atomic features by the method of Connectivity Matrix

    4.1.1. What needs to be tested.

     LBIFCPU SMC DRAM Peri GFX MPEG2 Video Audio HDMI

    (M2) (S1) CTL (S3) (M3) (S5) Output Output (S8) M1

    (S2) (S4) (S6) (S7)

    LBIF - × ? ? ? ? ? ? ? ?

    ?Copyright 2004 Be One Lab Inc (All Rights Reserved) 4

     SOC Design Verification Whitepaper

    (M1) M1_S1 M1_S2 M1_S3 M1_S4 M1_S5 M1_S6 M1_S7 M1_S8 CPU - - ? ? ? ? ? ? ? ? (M2) M2_S1 M2_S2 M2_S3 M2_S4 M2_S5 M2_S6 M2_S7 M2_S8 SMC - - - × × × × × × × (S1)

    DRAM - - - - × ? ? ? ? × CTL M3_S2 S5_S2 S6_S2 S7_S2 (S2)

    Peri - - - - - × × × × × (S3)

    GFX - - - - - - × × × × (M3)

    (S4)

    MPEG2 - - - - - - - ? × ? (S5) S5_S6 S5_S8 Video - - - - - - - - × × Output

    (S6)

    Audio - - - - - - - - - × Output

    (S7)

    HDMI - - - - - - - - - - (S8)

    4.1.2. Feature Coverage Matrix

    Feature Coverage Owner Status (example shown) M1_S1 UNDONE c_lbif_smc

    M1_S2 PASSED c_lbif_dram

    M1_S3 c_lbif_peri

    M1_S4 c_lbif_gfx

    M1_S5 c_lbif_mpeg2

    M1_S6 c_lbif_vout

    M1_S7 c_lbif_aout

    M1_S8 c_lbif_hdmi

    M2_S1 c_cpu_smc

    M2_S2 c_cpu_dram

    M2_S3 c_cpu_peri

    M2_S4 c_cpu_gfx

    M2_S5 c_cpu_mpeg2

    ?Copyright 2004 Be One Lab Inc (All Rights Reserved) 5

     SOC Design Verification Whitepaper

M2_S6 c_cpu_vout

    M2_S7 c_cpu_aout

    M2_S8 c_cpu_hdmi

    M3_S2 c_gfx_dram

    S5_S2 c_mpeg2_dram

    S6_S2 c_vout_dram

    S7_S2 c_aout_dram

    S5_S6 c_mpeg2_vout

    S5_S8 c_mpeg2_hdmi

4.2. Inter-Atomic features by the method of Interactivity Matrix

    4.2.1. What needs to be tested. Here we starts from 1 master and goes through several slaves whose

    functions interact with other slaves. Since LBIF/CPU are symmetric in

    our design, we just need to analyze the CPU master.

     SMC DRAM Peri GFX MPEG2 Video Audio HDMI

    (S1) CTL (S3) (S4) (S5) Output Output (S8)

    (S2) (S6) (S7)

    inter_S1_S2_S3 ? ? ?

    (remap)

    inter_s4_s6 ? ? ? inter_s4_s8 (gfx_out)

    inter_s5_s6 ? ? ? inter_s5_s8 (video_out)

    inter_s4_s5_s6 ? ? ? ? inter_s4_s5_s8 (gfx_video_out)

    inter_s5_s7 ? ? ? inter_s5_s8 (audio_out)

    Inter_s4_s5_s6_s7 ? ? ? ? ? Inter_s4_s5_s6_s8 (gfx_video_audio)

?Copyright 2004 Be One Lab Inc (All Rights Reserved) 6

     SOC Design Verification Whitepaper

    4.2.2. Feature Coverage Matrix

    Feature Coverage Owner Status (example shown) inter_S1_S2_S3 UNDONE c_remap

    (remap)

    inter_s4_s6 PASSED c_gfx_out

    inter_s4_s8

    (gfx_out)

    inter_s5_s6 c_video_out

    inter_s5_s8

    (video_out)

    inter_s4_s5_s6 c_gfx_video_out

    inter_s4_s5_s8

    (gfx_video_out)

    inter_s5_s7 c_audio_out

    inter_s5_s8

    (audio_out)

    Inter_s4_s5_s6_s7 c_gfx_video_audio

    Inter_s4_s5_s6_s8

    (gfx_video_audio)

4.3. Features by the method of Shared Resource

    4.3.1. Atomic features on Memory What needs to be tested.

Atomic Single port active

    ; All modes must be tested.

    ; Range should be fully tested if possible. Otherwise [Min, Max] region

    and random should be used.

    ; Random access sequences should be tested. Port Access_Mode Access_Range Access_Random_Sequence Mem_TS_RW

    Mem_M2VD_STR Mem_M2VD_UDW ?Copyright 2004 Be One Lab Inc (All Rights Reserved) 7

     SOC Design Verification Whitepaper

    Mem_M2VD_FRR Mem_M2VD_FRW Mem_VMIPS_FMR Mem_ADEC_STR

     Mem_DSP_GFX1R

     Mem_DSP_GFX2R

     Mem_DSP_VIDR

     Mem_SYS1_RW

     Mem_SYS2_RW

Feature Coverage Matrix

    Feature Coverage Owner Status (example shown) Mem_TS_RW UNDONE c_mem_ts_rw

    Mem_M2VD_STR PASSED c_mem_m2vd_str

    Mem_M2VD_UDW c_mem_m2vd_udw

    Mem_M2VD_FRR c_mem_m2vd_frr

    Mem_M2VD_FRW c_mem_m2vd_frw

    Mem_VMIPS_FMR c_mem_vmips_fmr

    Mem_ADEC_STR c_mem_adec_str

     Mem_DSP_GFX1R c_mem_dsp_gfx1r

     Mem_DSP_GFX2R c_mem_dsp_gfx2r

     Mem_DSP_VIDR c_mem_dsp_vidr

     Mem_SYS1_RW c_mem_sys1_rw

     Mem_SYS2_RW c_mem_sys2_rw

    4.3.2. Inter-Atomic features on Memory What needs to be tested.

    Inter-Atomic Multiple port active

    ; Arbitration scheme works correctly among multiple ports.

    ; Random access sequences should be tested. ?Copyright 2004 Be One Lab Inc (All Rights Reserved) 8

     SOC Design Verification Whitepaper

Feature Coverage Matrix

Feature Coverage Owner Status (example shown)

    Mem_arbitor UNDONE c_mem_arbitor

    Mem_random PASSED c_mem_random

4.3.3. Asynchronous timing feature by the method of fault model from Virgo

    project at DDR2 interface

    What needs to be tested.

    ; We developed a fault model against an asynchronous timing behavior on

    the DDR2 interface.

    Feature Coverage Matrix

Feature Coverage Owner Status (example shown)

    Mem_async_timing UNDONE c_mem_async_timing

4.3.4. Features on Memory Map Access

    Feature Coverage Matrix

Feature Coverage Owner Status

    Mem_Init c_mem_init

    Mem_walkthrough c_mem_walkthrough

    (Full, [min, max],

    random)

Mem_aliasing c_mem_aliasing

    (write to X does

    not affect Y)

    ?Copyright 2004 Be One Lab Inc (All Rights Reserved) 9

     SOC Design Verification Whitepaper

Mem_ghost c_mem_ghost

    (invalid address)

    4.3.5. Features on Register Map Access Feature Coverage Matrix

Feature Coverage Owner Status

    Reg_reset_value c_reg_reset

    Reg_rw_walkthrough c_reg_ rw_walkthrough

    (all R/W/RO/WO bits

    are correct)

    Reg_aliasing c_reg_aliasing

    (write to X does not

    affect Y)

    Reg_Ghost c_reg_ghost

    (invalid address)

4.4. Features by the method of Bus Hardening

    4.4.1. What needs to be tested.

    The following features must be covered:

    ; All bus access modes must be tested.

    ; All bus access ranges should be tested.

     all master/slave has to be exercised.

     [min, max], random, invalid (if allowed) address has to be exercised.

    ; Random access sequences should be tested.

4.4.2. Feature Coverage Matrix

Feature Coverage Owner Status

    Bus_mode c_bus_mode

    Bus_range c_bus_range

    ?Copyright 2004 Be One Lab Inc (All Rights Reserved) 10

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