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SBCARM7FLASHBASE

By Donald Cook,2014-08-27 14:20
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SBCARM7FLASHBASE

     /* sbcarm7.h - WindRiver SBC ARM7 header file */

    /* Copyright 1984-2001 Wind River Systems, Inc. */ #include "copyright_wrs.h"

/*

    modification history

    --------------------

    01f,16jul02,m_h C++ protection

    01e,04jan02,m_h minor cleanup

    01d,03dec01,m_h remove Diab warnings

    01c,27sep01,m_h base MAC address on user DIP setting 01b,22may01,m_h documentation

    01a,12apr01,m_h created from snds100 template. */

/*

    This file contains I/O address and related constants for the SBC ARM7 board.

    */

#ifndef INCsbcarm7h

    #define INCsbcarm7h

#ifdef __cplusplus

    extern "C" {

    #endif

#include "sngks32c.h"

#define TARGET_SBCARM7

/*****我修改成和config.h#define ROM_BASE_ADRS 0x02000000 一致***/

#define SBCARM7_FLASH_BASE 0x2000000

/*

     * Local-to-Bus memory address constants:

     * the local memory address always appears at 0 locally;

     * it is not dual ported.

     */

    #define LOCAL_MEM_LOCAL_ADRS 0x00000000 /* fixed */

#define LOCAL_MEM_BUS_ADRS 0x00000000 /* fixed */

#define BUS BUS_TYPE_NONE

    #define SBCARM7_CPU_SPEED 50000000 /* CPU clocked at 50 MHz. The timer */

     /* speed is related to this */

/* definitions for the KS32C50100 UART */

    #define N_SBCARM7_UART_CHANNELS 2 /* number of SBCARM7 UART chans */

    #define N_SIO_CHANNELS N_SBCARM7_UART_CHANNELS

    #define N_UART_CHANNELS N_SBCARM7_UART_CHANNELS

    #define UART_REG_ADDR_INTERVAL 1 /* registers 4 bytes apart */

/*去掉一下3个语句;*/

    /* LED Registers (write) */

    /*#define SBCARM7_LEDREG 0x3fd4000*/

/* USER DIP switch (read) */

    /*#define SBCARM7_USERREG 0x3fd4000

    #define READ_USERDIP() (*((volatile char *)SBCARM7_USERREG) & 0xff) */

    /*************************************************************************

     *

     * DRAM Memory Bank 0 area MAP for Exception vector table

     * and Stack, User code area.

     *

     */

    #define DRAM_BASE 0x0 /* Final start address of DRAM */ #define DRAM_LIMIT 0x2000000 /*old value = 0x400000 */ #define RESET_DRAM_START 0x100000 /* Start of DRAM on power-up old value = 0x1000000*/

    #define RESET_ROM_START 0x0 /* Start of ROM on power-up */

    /****************************************************************************

     *

     * Format of the Program Status Register

     */

#define FBit 0x40

    #define IBit 0x80

    #define LOCKOUT 0xC0 /* Interrupt lockout value */ #define LOCK_MSK 0xC0 /* Interrupt lockout mask value */ #define MODE_MASK 0x1F /* Processor Mode Mask */ #define UDF_MODE 0x1B /* Undefine Mode(UDF) */ #define ABT_MODE 0x17 /* Abort Mode(ABT) */ #define SUP_MODE 0x13 /* Supervisor Mode (SVC) */ #define IRQ_MODE 0x12 /* Interrupt Mode (IRQ) */ #define FIQ_MODE 0x11 /* Fast Interrupt Mode (FIQ) */ #define USR_MODE 0x10 /* User Mode(USR) */

/*************************************************************************

     * SYSTEM CLOCK

     */

#define MHz 1000000

    #define fMCLK_MHz 50000000 /* 50MHz, KS32C50100*/ #define fMCLK 50 /* fMCLK_MHz/MHz */

/*************************************************************************

     * SYSTEM MEMORY CONTROL REGISTER EQU TABLES

     */

/* SYSCFG Register Value */

    #define SYSCONFIG_VAL 0x07ffffa0 /* System Configuration Value, EDO

    RAM */

    #define SYSCONFIG_VAL_SDRAM 0xe7ffffa0 /* System Configuration Value,

    SDRAM old value=87ffffa0*/

    /* CLKCON Clock configuration register Values */ #define tCDIV (1<<0)

    #define tWE (0<<16)

    #define tMUX (0<<17)

    #define tAC (0<<18)

    #define tTEST (0<<31)

#define rCLKCON (tCDIV+tWE+tMUX+tAC+tTEST)

    /* EXTACONx External I/O access timing register Values */ #define tCOS0 (7<<0)

    #define tACS0 (7<<3)

#define tCOH0 (7<<6)

    #define tACC0 (7<<9)

    #define tCOS1 (1<<16)

    #define tACS1 (1<<19)

    #define tCOH1 (1<<22)

    #define tACC1 (1<<25)

#define rEXTACON0 (tCOS0+tACS0+tCOH0+tACC0+tCOS1+tACS1+tCOH1+tACC1)

#define tCOS2 (7<<0)

    #define tACS2 (7<<3)

    #define tCOH2 (7<<6)

    #define tACC2 (1<<9)

    #define tCOS3 (1<<16)

    #define tACS3 (1<<19)

    #define tCOH3 (1<<22)

    #define tACC3 (3<<25)

#define rEXTACON1 (tCOS2+tACS2+tCOH2+tACC2+tCOS3+tACS3+tCOH3+tACC3)

/***********************************************************

     *

     * -> EXTDBWTH : Memory Bus Width register

     */

    #define DSR0 (3<<0) /* ROM0, 0 : Disable, 1 : Byte etc.*/

    #define DSR1 (3<<2) /* ROM1 32 */

    #define DSR2 (1<<4) /* ROM2 */ #define DSR3 (0<<6) /* ROM3 */ #define DSR4 (0<<8) /* ROM4 */ #define DSR5 (0<<10) /* ROM5 */ #define DSD0 (3<<12) /* DRAM0 32 */

    #define DSD1 (0<<14) /* DRAM1 */ #define DSD2 (0<<16) /* DRAM2 */ #define DSD3 (0<<18) /* DRAM3 */ #define DSX0 (2<<20) /* EXTIO0 LCD接口 16*/

    #define DSX1 (1<<22) /* EXTIO1 USB接口 8*/

    #define DSX2 (1<<24) /* EXTIO2 以太网接口 16*/

    #define DSX3 (1<<26) /* EXTIO3*/

#define rEXTDBWTH

    (DSR0+DSR1+DSR2+DSR3+DSR4+DSR5+DSD0+DSD1+DSD2+DSD3+DSX0+DSX1+DSX2

    +DSX3)

/***********************************************************

     *

     * -> ROMCON0 : ROM Bank0 Control register

     */

    #define ROMBasePtr0 (0x0<<10) /*=0x00000000*/ #define ROMBasePtr0_S (0x200<<10) /*=0x02000000*/ #define ROMEndPtr0 ((ROM_SIZE>>16)<<20) /*=0x00100000*/ #define ROMEndPtr0_S (((ROM_SIZE>>16)+0x200)<<20) /*=0x02100000*/ #define PMC0 0x0 /* 0x0=Normal ROM, 0x1=4Word Page etc.*/ #define rTpa0 (0x0<<2) /* 0x0=5Cycle, 0x1=2Cycle etc.*/ #define rTacc0 (0x6<<4) /* 0x0=Disable, 0x1=2Cycle etc.*/ #define rROMCON0 (ROMEndPtr0+ROMBasePtr0+rTacc0+rTpa0+PMC0) #define rROMCON0_S (ROMEndPtr0_S+ROMBasePtr0_S+rTacc0+rTpa0+PMC0)

    /***************************************************************************

     * -> ROMCON1 : ROM Bank1 Control register, Mailbox Interface

     */

    #define ROMBasePtr1 (0x210<<10) /*=0x0fc0000*/ #define ROMEndPtr1 (((0x400000>>16)+0x210)<<20) /*=0x02500000*/ #define PMC1 0x0 /* 0x0=Normal ROM, 0x1=4Word Page etc.*/ #define rTpa1 (0x0<<2) /* 0x0=5Cycle, 0x1=2Cycle etc.*/ #define rTacc1 (0x6<<4) /* 0x0=Disable, 0x1=2Cycle etc.*/ #define rROMCON1 (ROMEndPtr1+ROMBasePtr1+rTacc1+rTpa1+PMC1)

    /***************************************************************************

     * -> ROMCON2 : ROM Bank2 Control register, EEPROM

     */

    #define ROMBasePtr2 (0x3fb<<10) /*=0x0fb0000*/ #define ROMEndPtr2 ((0xfc0000>>12)<<20) /*=0x0fc0000*/ #define PMC2 0x0 /* 0x0=Normal ROM, 0x1=4Word Page etc.*/ #define rTpa2 (0x0<<2) /* 0x0=5Cycle, 0x1=2Cycle etc.*/ #define rTacc2 (0x6<<4) /* 0x0=Disable, 0x1=2Cycle etc.*/ /* #define rROMCON2 (ROMEndPtr2+ROMBasePtr2+rTacc2+rTpa2+PMC2) */

    /***************************************************************************

     * -> ROMCONx : unused ROM Bank Control registers

     */

#define rROMCON2 0x60 /* add by ghw*/

    #define rROMCON3 0x60

    #define rROMCON4 0x60

    #define rROMCON5 0x60

/*ROMEndPtr5+ROMBasePtr5+rTacc5+rTpa5+PMC5*/

    /****************************************************************************

     * -> DRAMCON0 : RAM Bank0 control register (EDO)

     */

    #define EDO_Mode0 1 /*(EDO)0=Normal, 1=EDO DRAM*/ #define CasPrechargeTime0 1 /*(Tcp)0=1cycle,1=2cycle*/ #define CasStrobeTime0 2 /*(Tcs)0=1cycle ~ 3=4cycle*/ #define DRAMCON0Reserved 1 /* Must be set to 1*/ #define RAS2CASDelay0 0 /*(Trc)0=1cycle,1=2cycle*/ #define RASPrechargeTime0 2 /*(Trp)0=1cycle ~ 3=4clcyle*/ #define DRAMBasePtr0 (0x10<<10) /*=0x1000000 */

    #define DRAMBasePtr0_S 0x00 /* now RAM moved to zero */

    #define DRAMEndPtr0 (((LOCAL_MEM_SIZE >> 16) + 0x10) << 20) /*=0x02000000 - 32 MB */

    #define DRAMEndPtr0_S ((LOCAL_MEM_SIZE >> 16) << 20) /*=0x02000000 - 32 MB */

    #define NoColumnAddr0 2 /*0=8bit,1=9bit,2=10bit,3=11bits*/

#define Tcs0 (CasStrobeTime0<<1)

    #define Tcp0 (CasPrechargeTime0<<3)

    #define dumy0 (DRAMCON0Reserved<<4) /*dummy cycle*/ #define Trc0 (RAS2CASDelay0<<7)

    #define Trp0 (RASPrechargeTime0<<8)

    #define CAN0 (NoColumnAddr0<<30)

#define rDRAMCON0

    (CAN0+DRAMEndPtr0+DRAMBasePtr0+Trp0+Trc0+Tcp0+Tcs0+dumy0+EDO_Mode0) #define rDRAMCON0_S

    (CAN0+DRAMEndPtr0_S+DRAMBasePtr0_S+Trp0+Trc0+Tcp0+Tcs0+dumy0+EDO_Mode0)

    /****************************************************************************

     * -> DRAMCONx : unused RAM Banks

     */

    #define rDRAMCON1 0x00

    #define rDRAMCON2 0x00

    #define rDRAMCON3 0x00

    /****************************************************************************

     * -> DRAMCON0 : RAM Bank0 control register (for SDRAM)

     */

    #define SRAS2CASDelay0 1 /*(Trc)0=1cycle,1=2cycle*/ #define SRASPrechargeTime0 3 /*(Trp)0=1cycle ~ 3=4cycle*/ #define SCasPrechargeTime0 1 /*(Tcp)0=1cycle,1=2cycle*/ #define SCasStrobeTime0 2 /*(Tcs)0=1cycle ~ 3=4cycle*/ #define SNoColumnAddr0 1

    /*0=8bit,1=9bit,2=10bit,3=11bits add by ghw*/

    #define SCAN0 (SNoColumnAddr0<<30)

    #define STrc0 (SRAS2CASDelay0<<7)

    #define STrp0 (SRASPrechargeTime0<<8)

    #define STcp0 (SCasPrechargeTime0<<3)

    #define STcs0 (SCasStrobeTime0<<1)

#define rSDRAMCON0

    (SCAN0+DRAMEndPtr0+DRAMBasePtr0+STrp0+STrc0+STcp0+STcs0)

    #define rSDRAMCON0_S

    (SCAN0+DRAMEndPtr0_S+DRAMBasePtr0_S+STrp0+STrc0+STcp0+STcs0)

    /****************************************************************************

     * -> DRAMCONx : unused SYNC DRAM Banks

     */

    #define rSDRAMCON1 0x00

    #define rSDRAMCON2 0x00

    #define rSDRAMCON3 0x00

    /**************************************************************************

     * -> REFEXTCON : External I/O & Memory Refresh cycle Control Register

     */

    #define RefCycle 16 /*Unit [us], 1k refresh 16ms*/

/*RefCycle EQU 8 ;Unit [us], 1k refresh 16ms*/

    #define CASSetupTime 0 /*0=1cycle, 1=2cycle*/ #define CASHoldTime 0 /*0=1cycle, 1=2cycle, 2=3cycle,

     3=4cycle, 4=5cycle,*/ #if (((2<<11)+1-(RefCycle*fMCLK)) < 0x3FF)

    #define RefCycleValue (((2<<11)+1-(RefCycle*fMCLK))<<21) #else

    #define RefCycleValue (0x3FF<<21)

    #endif

#define Tcsr (CASSetupTime<<20) /* 1cycle */

    #define Tcs (CASHoldTime<<17)

    #define ExtIOBase 0x183fd /* Refresh enable, VSF=1*/

    #define rREFEXTCON (RefCycleValue+Tcsr+Tcs+ExtIOBase)

    /******************************************************************

     *SRefCycle EQU 16 ;Unit [us], 4k refresh 64ms

     */

    #define SRefCycle 8 /*Unit [us], 4k refresh 64ms*/ #define ROWcycleTime 3 /*0=1cycle, 1=2cycle, 2=3cycle,

     3=4cycle, 4=5cycle,*/ #define SRefCycleValue ((2048+1-(SRefCycle*fMCLK))<<21) #define STrc (ROWcycleTime<<17)

    #define rSREFEXTCON (SRefCycleValue+STrc+ExtIOBase)

/* interrupt levels */

    #define INT_LVL_EXTINT0 0 /* External Interrupt0 */ #define INT_LVL_EXTINT1 1 /* External Interrupt1 */ #define INT_LVL_EXTINT2 2 /* External Interrupt2 */ #define INT_LVL_EXTINT3 3 /* External Interrupt3 */ #define INT_LVL_UARTTX0 4 /* UART 0 Transmit Interrupt */ #define INT_LVL_UARTRX0 5 /* UART 0 Receive & Error Interrupt */ #define INT_LVL_UARTTX1 6 /* UART 1 Transmit Interrupt */ #define INT_LVL_UARTRX1 7 /* UART 1 Receive & Error Interrupt */ #define INT_LVL_GDMA0 8 /* GDMA channel 0 interrupt*/ #define INT_LVL_GDMA1 9 /* GDMA channel 1 interrupt */ #define INT_LVL_TIMER0 10 /* Timer 0 Interrupt */ #define INT_LVL_TIMER1 11 /* Timer 1 Interrupt */ #define INT_LVL_HDLCTxA 12 /* HDLC channel A Tx interrupt*/ #define INT_LVL_HDLCRxA 13 /* HDLC channel A Rx interrupt*/ #define INT_LVL_HDLCTxB 14 /* HDLC channel B Tx interrupt*/ #define INT_LVL_HDLCRxB 15 /* HDLC channel B Rx interrupt*/ #define INT_LVL_BDMATx 16 /* Ethernet controller BDMA Tx Interrupt */ #define INT_LVL_BDMARx 17 /* Ethernet controller BDMA Rx Interrupt */ #define INT_LVL_MACTx 18 /* Ethernet controller MAC Tx Interrupt*/ #define INT_LVL_MACRx 19 /* Ethernet controller MAC Rx Interrupt */ #define INT_LVL_IIC 20 /* IIC -Bus Interrupt */

/* interrupt vectors */

    #define INT_VEC_EXTINT0 IVEC_TO_INUM(INT_LVL_EXTINT0) /* External Interrupt0 */

    #define INT_VEC_EXTINT1 IVEC_TO_INUM(INT_LVL_EXTINT1) /* External Interrupt1*/

    #define INT_VEC_EXTINT2 IVEC_TO_INUM(INT_LVL_EXTINT2) /* External

Interrupt2*/

    #define INT_VEC_EXTINT3 IVEC_TO_INUM(INT_LVL_EXTINT3) /* External Interrupt3*/

    #define INT_VEC_UARTTX0 IVEC_TO_INUM(INT_LVL_UARTTX0) /* UART 0 Transmit Interrupt */

    #define INT_VEC_UARTRX0 IVEC_TO_INUM(INT_LVL_UARTRX0) /* UART 0 Receive & Error Interrupt */

    #define INT_VEC_UARTTX1 IVEC_TO_INUM(INT_LVL_UARTTX1) /* UART 1 Transmit Interrupt */

    #define INT_VEC_UARTRX1 IVEC_TO_INUM(INT_LVL_UARTRX1) /* UART 1 Receive & Error Interrupt */

    #define INT_VEC_GDMA0 IVEC_TO_INUM(INT_LVL_GDMA0) /* GDMA channel 0 interrupt*/

    #define INT_VEC_GDMA1 IVEC_TO_INUM(INT_LVL_GDMA1) /* GDMA channel 0 interrupt*/

    #define INT_VEC_TIMER0 IVEC_TO_INUM(INT_LVL_TIMER0) /* Timer 0 Interrupt */

    #define INT_VEC_TIMER1 IVEC_TO_INUM(INT_LVL_TIMER1) /* Timer 1 Interrupt */

    #define INT_VEC_HDLCTxA IVEC_TO_INUM(INT_LVL_HDLCTxA) /* HDLC channel A Tx interrupt */

    #define INT_VEC_HDLCRxA IVEC_TO_INUM(INT_LVL_HDLCRxA) /* HDLC channel A Rx interrupt*/

    #define INT_VEC_HDLCTxB IVEC_TO_INUM(INT_LVL_HDLCTxB) /* HDLC channel B Tx interrupt*/

    #define INT_VEC_HDLCRxB IVEC_TO_INUM(INT_LVL_HDLCRxB) /* HDLC channel B Rx interrupt*/

    #define INT_VEC_BDMATx IVEC_TO_INUM(INT_LVL_BDMATx) /* Ethernet controller BDMA Tx Interrupt */

    #define INT_VEC_BDMARx IVEC_TO_INUM(INT_LVL_BDMARx) /* Ethernet controller BDMA Rx Interrupt */

    #define INT_VEC_MACTx IVEC_TO_INUM(INT_LVL_MACTx) /* Ethernet controller MAC Tx Interrupt*/

    #define INT_VEC_MACRx IVEC_TO_INUM(INT_LVL_MACRx) /* Ethernet controller MAC Rx Interrupt */

    #define INT_VEC_IIC IVEC_TO_INUM(INT_LVL_IIC) /* IIC -Bus Interrupt */

    /**********************************************************************************************************

     * Cache Definitions

     *

     */

#define NON_CACHE_REGION 0x4000000

    #define SBCARM7_CACHE_ENABLE 0x02

    #define SBCARM7_CACHE_4K 0x00

    #define SBCARM7_CACHE_8K 0x10

    #define SBCARM7_CACHE_MODE 0x30

    #define SBCARM7_WRITE_BUFF 0x04

    #define SBCARM7_TAGRAM 0x11000000

/*

     *

     * definitions for the SBCARM7 Timer:

     * two timers clocked from same source and with the same reload overhead

     */

    #define SBCARM7_TIMER_SYS_TC_DISABLE (TC_DISABLE | TC_PERIODIC | TC_DIV16)

    #define SBCARM7_TIMER_SYS_TC_ENABLE (TC_ENABLE | TC_PERIODIC | TC_DIV16)

    #define SBCARM7_TIMER_AUX_TC_DISABLE (TC_DISABLE | TC_PERIODIC | TC_DIV16)

    #define SBCARM7_TIMER_AUX_TC_ENABLE (TC_ENABLE | TC_PERIODIC | TC_DIV16)

    #define SYS_TIMER_CLK (SBCARM7_CPU_SPEED) /* Frequency of counter/timer */

    #define AUX_TIMER_CLK (SBCARM7_CPU_SPEED) /* Frequency of counter/timer */

    #define SBCARM7_RELOAD_TICKS 3 /* three ticks to reload timer */

    #define SYS_TIMER_CLEAR(x) (SBCARM7_TIMER_T1CLEAR(x)) /* sys Clk is timer 1 */

    #define SYS_TIMER_CTRL(x) (SBCARM7_TIMER_T1CTRL(x)) #define SYS_TIMER_LOAD(x) (SBCARM7_TIMER_T1LOAD(x)) #define SYS_TIMER_VALUE(x) (SBCARM7_TIMER_T1VALUE(x)) #define SBCARM7_TIMER_VALUE_MASK 0xFFFF

    #define AUX_TIMER_CLEAR(x) (SBCARM7_TIMER_T2CLEAR(x)) /* aux Clk is timer 2 */

    #define AUX_TIMER_CTRL(x) (SBCARM7_TIMER_T2CTRL(x)) #define AUX_TIMER_LOAD(x) (SBCARM7_TIMER_T2LOAD(x)) #define AUX_TIMER_VALUE(x) (SBCARM7_TIMER_T2VALUE(x))

#define SYS_TIMER_INT_LVL (INT_LVL_TIMER0)

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