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VHDLsy

By Donald Fox,2014-06-13 20:05
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VHDLsy

1.2 D????Æ?µÄÉè?Æ

    library ieee;

    use ieee.std_logic_1164.all; entity d_chufa is

     port ( clk,d:in std_logic;

     q:out std_logic); end d_chufa;

    architecture behav of d_chufa is begin

    process(clk)is

    begin

    if(clk 'event and clk='1')then q<=d;

    end if;

    end process;

    end behav;

1.3?øÓÐÒì??ÇåÁã??Òì??ÖÃÎ???ÄܵÄ?ßÑØJK????Æ?µÄÉè?Æ??

    library ieee;

    use ieee.std_logic_1164.all; entity jk is

    port( pset,clr,clk,j,k:in std_logic;

     q,qb:out std_logic); end entity;

    architecture behav of jk is signal q_s,qb_s:std_logic; begin

    process(pset,clr,clk,j,k) begin

    if(pset='0')and(clr='1')then q_s<='1';qb_s<='0';

    elsif(pset='1')and(clr='0')then q_s<='0';qb_s<='1';

    elsif(clk 'event and clk='1')then if(j='0')and(k='1')then q_s<='0';qb_s<='1';

    elsif(j='1')and(k='0')then q_s<='1';qb_s<='0';

    elsif(j='1')and(k='1')then q_s<=not q_s;

    qb_s<=not qb_s;

    end if;

    end if;

    q<=q_s;

qb<=qb_s;

    end process;

    end behav;

2.1ʵÏÖ?ë?ÓÓë?ë?õµÄ??ÄÜ

    ???Ó??Óë?õ??Çø?Ö?ÉÁ??ö??ÄÜÄ??é??Ê?ÓÃBLOCKÓï?ä????ÔìÌå?ÖΪÁ??ó???Ö

    library ieee;

    use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity half is

     port ( a,b:in std_logic;

     sum,car,dif,bor:out std_logic); end half;

    architecture behav of half is begin

    g1:block

    begin

    sum<=a xor b;

    car<=a xor b;

    end block g1;

    g2:block

    begin

    dif<=a xor b;

    bor<=(not a) and b;

    end block g2;

    end behav;

    2.2 4Î?Ë?ÏòÍ?ÓÃÒÆÎ??Ä?æÆ?74LS194 library ieee;

    use ieee.std_logic_1164.all; entity ls194 is

     port ( clr,s0,s1,clk,l,r:in std_logic;

     p:in std_logic_vector(3 downto 0);

     q:out std_logic_vector(3 downto 0)); end ls194;

    architecture behav of ls194 is signal qs:std_logic_vector(3 downto 0); begin

    process(clr,s0,s1,clk,l,r)is begin

    if(clr='0')then

    qs<="0000";

    elsif(clk 'event and clk='1')then

     if(s1='1')and(s0='1')then qs<=p;

     elsif(s1='0')and(s0='1')then

     if(r='1')then qs(3)<='1';

     qs(2 downto 0)<=qs(3 downto 1);

     elsif(r='0')then qs(3)<='0';

     qs(2 downto 0)<=qs(3 downto 1);

     end if;

     elsif(s1='1')and(s0='0')then

     if(l='1')then qs(0)<='1';

     qs(3 downto 1)<=qs(2 downto 0);

     elsif(l='0')then qs(0)<='0';

     qs(3 downto 1)<=qs(2 downto 0);

     end if;

     end if;

    end if;

    q<=qs;

    end process;

    end behav;

2.3Éè?ÆÒ??ö4Î??Ó?õ??Æ?.

    library ieee;

    use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity subadd is

    port(sub:in std_logic;

     a,b:in std_logic_vector(3 downto 0);

     s:out std_logic_vector(3 downto 0);

     co:out std_logic);

    end entity subadd;

    architecture behav of subadd is signal temp:std_logic_vector(4 downto 0);

    begin

    process(sub,a,b)

     begin

     if sub='1' then

     temp<=a+b;

     else

     temp<=a-b;

     end if;

    end process;

    s<=temp(3 downto 0);

    co<=temp(4);

    end behav;

    3.1 3?Á8ÒëÂëÆ?µÄÉè?Æ??ÓÃWITH?ªSELECTÓï?äÍê?É??EN??1Ê?Õý????×???

    EN=0Ê?????×?

library ieee;

    use ieee.std_logic_1164.all;

    entity decode3to8 is

    port(a:in std_logic_vector(2 downto 0);

     en:in std_logic;

     y:out std_logic_vector(7 downto 0)); end decode3to8;

    architecture behav of decode3to8 is

     signal sel:std_logic_vector(3 downto 0); begin

     sel<=a&en;

     with sel select

     Y<= "00000001" when "0001",

     "00000010" when "0011",

     "00000100" when "0101",

     "00001000" when "0111",

     "00010000" when "1001",

     "00100000" when "1011",

     "01000000" when "1101",

     "10000000" when "1111",

     "XXXXXXXX" when others; end behav;

3.2

    4Î?Êý?ÝÊäÈë???É?íÊ?0?ª?ªFÊ?Áù?öÊýÖµ????ÆäÒëÂëΪ??Òõ??7?ÎLEDµÄÏÔÊ?Â

    ë

    library ieee;

    use ieee.std_logic_1164.all;

    entity leddecoder is

     port(i:in std_logic_vector(3 downto 0);

     dout:out std_logic_vector(0 to 6)); end leddecoder;

    architecture behav of leddecoder is begin

    process(i)

    begin

    case i is

    when "0000"=>dout<="1111110"; when "0001"=>dout<="0110000"; when"0010"=>dout<="1101101";

    when"0011"=>dout<="1111001";

    when"0100"=>dout<="0110011";

    when"0101"=>dout<="1011011";

    when"0110"=>dout<="1011111";

    when"0111"=>dout<="1110000"; when"1000"=>dout<="1111111"; when"1001"=>dout<="1111011"; when"1010"=>dout<="1110111"; when"1011"=>dout<="0011111"; when"1100"=>dout<="1001110"; when"1101"=>dout<="0111101"; when"1110"=>dout<="1001111"; when"1111"=>dout<="1000111"; when others=>dout<="0000000"; end case;

    end process;

    end behav;

    3.3Éè?ÆÍê?ÉÒ??ö7Î?µÄÅ?Í?Î??úÉúÆ? Êý?ÝÎ?ÓëÅ?Í?Î?µÄ1µÄ?öÊýΪÅ?Êý library ieee;

    use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity tongwei is

     port (

     a:in std_logic_vector(6 downto 0);

     c:out std_logic_vector(7 downto 0));

    end entity;

    architecture behav of tongwei is signal temp:std_logic;

    begin

    temp<=a(0)xor a(1)xor a(2)xor a(3)xor a(4)xor a(5)xor a(6);

    c<=a & temp;

    end behav;

4.1Íê?É1Î?È??ÓÆ?µÄÉè?Æ

    library ieee;

    use ieee.std_logic_1164.all; entity fulladd is

     port (

     a,b,c:in std_logic;

     car,s:out std_logic); end entity fulladd;

    architecture behav of fulladd is begin

    s<=a xor b xor c ;

    car<=(a and b)or(b and c)or(c and a);

end behav;

4.2Íê?É4Î?È??Ó??Æ?µÄÉè?Æ

    ÓÉ4?ö1Î?µÄÈ??Ó??Æ???Áª?ø?É

    library ieee;

    use ieee.std_logic_1164.all;

    use ieee.std_logic_arith.all;

    use ieee.std_logic_unsigned.all; entity fulladd4 is

    port( a,b:in std_logic_vector(3 downto 0);

     c0:in std_logic;

     s:out std_logic_vector(3 downto 0)); end entity;

    architecture str of fulladd4 is signal c1,c2,c3,c4:std_logic;

component fulladd

    port(a,b,c:in std_logic;

     car,s:out std_logic);

    end component;

    begin

    u1:

    fulladd port map(a(0),b(0),c0,c1,s(0)); u2:

    fulladd port map(a(1),b(1),c1,c2,s(1)); u3:

    fulladd port map(a(2),b(2),c2,c3,s(2)); u4:

    fulladd port map(a(3),b(3),c3,c4,s(3)); end architecture str;

4.3Éè?ÆÒ??ö3bitsµÄ?ÉÄæ?ÆÊýÆ?

    library ieee;

    use ieee.std_logic_1164.all;

    use ieee.std_logic_arith.all;

    use ieee.std_logic_unsigned.all; entity kenijishu is

     port ( dir,clk:in std_logic;

     q:out std_logic_vector (2 downto 0)); end entity;

    architecture behav of kenijishu is signal temp:std_logic_vector (2 downto 0); begin

     q<=temp;

     process(clk)

     begin

     if(clk 'event and clk='1')then

     if(dir='1')then

     temp<=temp+'1';

     else

     temp<=temp-'1';

     end if;

     end if;

     end process;

    end behav;

    5.1Éè?ÆÍê?ÉÒ?10?øÖÆ?Ó???ÆÊýÆ??? ÓÐÍ???ÖÃÊý??Í???ÇåÁãµÄ??ÄÜ library ieee;

    use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity count10 is

    port ( clr,clk,en:in std_logic;

     datain:in std_logic_vector(3 downto 0);

     co:out std_logic;

    dataout:out std_logic_vector(3 downto 0));

    end count10;

    architecture behav of count10 is signal tmp:std_logic_vector(3 downto 0);

    begin

    process(clk)

    begin

    if(clk 'event and clk='1')then if(clr='1')then

     tmp<="0000";

    elsif(en='1')then

     tmp<=datain;

    elsif(tmp="1001")then

     tmp<="0000";co<='1';

     else

     tmp<=tmp+1;co<='0';

     end if;

    end if;

    end process;

    dataout<=tmp;

     end behav;

    5.2Éè?ÆÍê?É100?øÖÆ?Ó???ÆÊýÆ???

ÒªÇó?º?ÉÓÃ??ÔìÌå?á????ÃèÊö??Ê?ÓÉ2?ö10?øÖÆ?ÆÊýÆ???Áª?ø?É

    library ieee;

    use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity count100 is

    port(clk:in std_logic;

     co:out std_logic;

     dout1,dout2:out std_logic_vector(3 downto 0));

    end count100;

    architecture behave of count100 is component count10 is

    port(clk:in std_logic;

     co:out std_logic;

     dataout:out std_logic_vector(3 downto 0));

    end component;

    signal temp:std_logic;

    begin

    u1:count10 port map(clk,temp,dout1); u2:count10 port map(temp,co,dout2); end behave;

    µ×?ãÎÄ?þ?º

    library ieee;

    use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity count10 is

    port(clk:in std_logic;

     co:out std_logic;

     dataout:out std_logic_vector(3 downto 0));

    end count10;

    architecture behave of count10 is signal temp:std_logic_vector(3 downto 0); begin

    dataout<=temp;

    process(clk)

    begin

    if(clk'event and clk='1')then

     if(temp="1001")then

     temp<="0000";

     co<='1';

     else

     temp<=temp+'1';

     co<='0';

     end if;

    end if;

end process;

    end behave;

1.1

    ?ÇÃÅ

    LIBRARY IEEE;

    USE IEEE.STD_LOGIC_1164.ALL; ENTITY NOT IS

     PORT(A:IN STD_LOGIC;

     Y:OUT STD_LOGIC); END ENTITY NOT;

    ARCHITECTURE ART OF NOT IS

     BEGIN

     Y<= NOT A;

     END ARCHITECTURE ART;

    Òì?òÃÅ

    LIBRARY IEEE;

    USE IEEE.STD_LOGIC_1164.ALL; ENTITY XOR2 IS

     PORT(A,B:IN STD_LOGIC;

     Y:OUT STD_LOGIC); END ENTITY XOR2;

    ARCHITECTURE ART OF XOR2 IS

     BEGIN

     Y<=A XOR B;

     END ARCHITECTURE ART;

    6.1ʵÑéÄÚÈÝ?ºLPMÕ×??ÄÜ?éµÄÊ?ÓÃ??

?ÔLPMÕ×??Äܵ?ÔªµÄlpm_fifoÄ??é?øÐкÏÀíµÄ?ÎÊýÉèÖÃ???èÖú?ÂÕæÊÖ?Î?ÖÎöÊ

    äÈë??Êä?ö?Ë?ÚµÄ??ÄÜ?????øÐÐ?òµ?µÄ˵Ã???

6.2ʵÑéÄÚÈÝ?º

     ÀûÓÃLPMÕ×??Äܵ?ÔªµÄlpm_fifoÄ??éʵÏÖ?ÔÁ?ÐøÊäÈëµÄÊý?ݵÄÑÓÊ???

    ÒªÇó?ºÊäÈëÊý?Ý?í?ÈΪ8Î???ÑÓÊ?Ê??äΪ5?öÊ?ÖÓÖÜÆÚ??

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