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4_PDMA

By Margaret Bennett,2014-06-18 04:47
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4_PDMA 4_PDMA 4_PDMA 4_PDMA 4_PDMA 4_PDMA

NuMicro Cortex-M0NuMicro Cortex-M0

PDMAPDMA

    议议议议

    特性

    方议议

    功能描述

    示例

    特性特性

    九通道 DMA (Peripheral-to-Memory or Memory-to-

    Peripheral or Memory-to-Memory)

    一个内部 word buffer

    源和目的地址有两种种种: 增加(固定

    种种种种种种度可以,8/16/32

    方议议SPI 0

    AHB

    SPI 1

    SPI 2 Master/Slave Wrapper

    CH0 ControlSPI 3

    GloConllerbal tro

    1 Word Buffer

    I/O, DecoderUART 0

    CH1 ControlRegisters

    UART 1

    1 Word Buffer

    USBBus MasterCH8 ControlADC

    Control

    1 Word Buffer

    I2S

    Memory-to-MemoryMemory-to-Memory

    从内内数存到存搬议据

    PDMA_SARx

    Source Addr.

    PDMA_DARxSource

     Destination Addr. PDMA

    Controller

    Channel xPDMA_BCRxDestination

    Byte Counter

    Memory

    Memory-to-APB IPMemory-to-APB IP

    从内存到 APB IP

    SAD_SEL

    Source Addr. Direction

    DAD_SELFixed or Incremental

    Dest. Addr. Direction

    Fixed

    PDMA

    ControllerSource Destination

    Channel x

    APB IP

    APB_TWS

    MemoryTransfer Width Select

    8/16/32-bits

    APB IP-to-Memory APB IP-to-Memory

    APB IP到存搬议据内数

    DAD_SEL

    Dest. Addr. DirectionSAD_SELFixed or IncrementalSource Addr. Direction

    Fixed

    PDMA

    ControllerSource Destination

    Channel x

    APB IP

    APB_TWS

    MemoryTransfer Width Select

    8/16/32-bits

BLKD: 议议议完成

TABORT: / 目议 Abort

例子

利用PDMASPI flash移议据到存数内

SPI0 作议主模式, 8bits 据议

PDMA 议议示例 (1/4)议议示例 PDMA (1/4)

    #defineTEST_LENGTH256

    uint8_t DestArray[TEST_LENGTH];

    volatile uint32_t PDMA0_INT_Flag;

    void PDMA0_Callback(void);

    int main(void)

    {

    STR_PDMA_T sPDMA;

    uint32_t SPIPort;

    Write locked register to initial HCLK

    /* Unlock the protected registers */

    UNLOCKREG();

    /* Enable the 12MHz oscillator oscillation */

    DrvSYS_SetOscCtrl(E_SYS_XTL12M, 1);

    /* HCLK clock source. 0: external 12MHz; 4:internal 22MHz RC oscillator */

    DrvSYS_SetHCLKSource(0);

    LOCKREG();

    /* HCLK clock frequency = HCLK clock source / (HCLK_N + 1) */

    DrvSYS_SetClockDivider(E_SYS_HCLK_DIV, 0);

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