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in circuit test

By Jacob Stevens,2014-06-30 06:26
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in circuit test

    ICT ( ) 在线测试

    z一种元器件级的测试方法用来测试

    装配后的电路板上的每个元器件.

    z如果功能测试是一种黑盒测试的话

    ,那么在线测试就是一种白盒测试.

    在线测试技术

    ICT "#$% Agilent3070

    ICT "#$% GenRad228x

    ICT "#$% Teradyne

    Spectrum

    PCB

    ICT TESTER

    ICT 简易示意图

    Fixture

    ICT的优点(相对于FT) * 统一的硬件平台 * 速度较快

    * 统一的流程

    * 故障定位精确

    * 能抓到电子隐性故障的唯一方法

    --易于投资

    --易于控制

    --当然,这决定于工程师的能力

    --维修费用较低

    --提高产品质量

    衡量ICT5大要素 * 测试覆盖率.

    * 稳定性

    * 测试时间.

    * 故障定位

    * 信息反馈

    AgilentICT Tester

    Agilent307x Series 3 Architecture

    TestheadLayout

    :Bank,Row,Column :20378,203178

    Configuring a Four-Module System

    Cards

    HybridPlusHybridPlusPin CardPin Card

    Double Density HybridDouble Density Hybrid

    ChannelPlusChannelPlusPin CardPin Card

    AccessPlusAccessPlusPin cardPin card

Analog Pin CardAnalog Pin Card

    Double Density Analog Pin CardDouble Density Analog Pin Card

    Serial Pin CardSerial Pin Card

    ASRU ASRU --Rev A,B or CRev A,B or C ControlControl

    ControlPlusControlPlus

    ControlXTControlXT

    Systemconfigfile

    PATH:/hp3070/diagnostic/th1/config testheadname "testhead1"

    line frequency 50

    relay 1 controls vacuum 2,3

    relay 2 controls vacuum 0,1

    bank 1

    module 0

    cards 1asru

    cards 2 hybrid advanced ! double density cards 3 hybrid advanced ! double density cards 4 hybrid advanced ! double density cards 5 hybrid advanced ! double density cards 6 control plus

    cards 7 hybrid advanced ! double density cards 8 hybrid advanced ! double density cards 9 hybrid advanced ! double density cards 10 hybrid advanced ! double density cards 11 hybrid advanced ! double density supplies hp6624 13 to 16 !asruchannels 1 to 4 ports ext7, ext8

    end module

    module 1

    …….

    End module

    end bank

    bank 2

    …… end bank

    Board levelconfigfile

    module 2

    cards 1asruc revision

    cards 2 hybrid standard double density cards 3 hybrid standard double density cards 4 hybrid standard double density cards 5 hybrid standard double density cards 6 control plus

    cards 7 hybrid standard double density !@ cards 8 hybrid standard double density !@ cards 9 hybrid standard double density !@ cards 10 hybrid standard double density !@ cards 11 hybrid standard double density supplies 5 to 8

    end module

    module 3

    cards 1asruc revision

    !@ cards 2 hybrid standard double density !@ cards 3 hybrid standard double density !@ cards 4 hybrid standard double density !@ cards 5 hybrid standard double density cards 6 control plus

    cards 7 hybrid standard double density cards 8 hybrid standard double density cards 9 hybrid standard double density cards 10 hybrid standard double density cards 11 hybrid standard double density supplies 1 to 4

    end module

    Short Wire Fixture Architecture

    Command controltesthead

    Testhead power on

    fix lock, fix unlock-----compressed air faon,faoff------Vacuum

    vacuum well is faon fbon

    Vacuum well a is 2,3

    Vacuum well bis 0,1

GenRad2287 tester

    GenRad Hardware OverviewGenRad Hardware Overview FixtureFixture

    GenRad RECEIVERGenRad RECEIVER

    PIN CARDPIN CARD

    REFERENCEREFERENCE

    C/S/TC/S/T

    RSTRST

    ICAICA

    Windows NTWindows NT

    MXI Bus

UUT PS

    IEE-488

    MTGMTG

    AFTM CARDAFTM CARD

    PIN CARDPIN CARD

    PIN CARDPIN CARD

    PIN CARDPIN CARD

    DSM BOARDDSM BOARD

    0 1 3 3 4 5 6 31 32 33 34

    PIN BAY

    MTG

    RTC

    CST

    AFTM

    Reference

    ICA

    DSM

    MXI to GenRad board

    Functional blocks are MXI to GR businterface Run Time Controller

    Bus interface for the analog subsystem directs & coordinaes pin

    board activities; data transfers between cpu and the digital

    subsystem

    Clock/synchronus/trigger board

    Privides event timing and event detection Driver/Sensor reference

    Supplies programmed dc reference voltages for the D/S pin

    boards

    DDeep Serial Memory

    Analog Functional Module

    - Analog Module

    SolectronConfidential

    GenRad

    228x Series

    Architecture

TESTPLANTESTPLAN

    …… call Pre_shorts

    …… call Shorts

    ……. Call Analog_tests

……

    Calltestjet

    ……

    Call digital

    ……

    Sub Characterize

    learn capacitance on

    learn capacitance off

    subend

    Sub Pre_Shorts

    ……… Subend

    Sub Shorts

     "shorts" Subend

    Sub Analog_Tests

     "analog/c4"

     "analog/r56" ……… subend

    ……… Sub Digital_Tests

     "digital/u1"

     "digital/u2" ……

    subend

    ………

Typical Example of Typical Example of Analog TestAnalog

    disconnect all

    connect s to !N1"

    connect I to !N2"

    connect g to !N100"

    resistor 10k, 5.5,5,re5,ar0.1

Resistor typical program:Resistor typical program:

    1. 1. S bus S bus

    2. I bus2. I bus

    3. G bus3. G bus

    4. A bus 4. A bus

5. B bus 5. B bus

    6. L bus6. L bus

    enhancement

    ZZcc=1/2=1/2ppffccC=1/2 C=1/2 ppffZZcc

    Capacitor :Capacitor :Inductor :Inductor :

    ZZL L =2=2ppffLL

    Capacitor

    !!!! 2 0 1 1002945327 0000

    ! IPG: rev B.03.42 Sat Oct 13 11:55:28 2001

    ! Common Lead Resistance 100m, Common Lead Inductance 1.00u ! Fixture: EXPRESS

    on failure

    report parallel devices

    report "r1 15.0k"

    end on failure

    disconnect all

    connect s to "GND"; a to "GND"

    connect i to "TREE__1022"

    connect g to "+5"

    capacitor 100n, 13.4, 8.66, fr1024, re3,wb, ar100m,sa, en, nocomp

    off failure

    Capacitor file

    Diode &ZenerTest

    !!!! 2 0 1 885232159 0000

    ! IPG: rev B.02.54 Mon Jan 19 09:49:20 1998

    ! Common Lead Resistance 500m, Common Lead Inductance 1.00u

    ! Fixture: EXPRESS

    disconnect all

    connect s to "VCC"

    connect i to "$34"

    diode 728m, 413m, idc5.0m, co3.0, ar828m

    Diode File

    FET Configuration

    !!!! 2 0 1 924217662 0000

    ! IPG: rev B.03.13 Wed Mar 31 11:25:15 1999

    ! Common Lead Resistance 500m, Common Lead Inductance 1.00u ! Fixture: EXPRESS

    on failure

    report parallel devices

    report "q23 q23:fet100, 20.0"

    end on failure

    disconnect all

connect s to "TREE89"

    connect i to "B0"

    connect g to "VF"

    nfetr81.6, 10.0, re1, ar50.0m

    FET File

     Options

Test Options

    amamplitude sause the A bus to sense the S bus

    arASRU range sbuse the B bus to sense the I bus

    idcDC current sluse the L bus to sense the G bus

    comp ----capacitor compensation

    enenhancement

    nocomp----No compensation

    edextra digit

    frfrequency

    co voltage compliance

    rereference elementicocurrent compliance

    wawaitwbwideband

TESTPLANTESTPLAN

    ……

    call Pre_shorts

    ……

    call Shorts

    …….

    Call Analog_tests

    ……

    Calltestjet

    ……

    Call digital

    ……

Sub Characterize

    learn capacitance on

    learn capacitance off

    subend

    Sub Pre_Shorts

    ……… Subend

    Sub Shorts

     "shorts" Subend

    Sub Analog_Tests

     "analog/c4"

     "analog/r56" ……… subend

    ……… Sub Digital_Tests

     "digital/u1"

     "digital/u2" ……

    subend

    ……… The parts of a Digital TestThe parts of a Digital

    ! Declaration Section

    ! Device Type

    ! assignment section

    ! Timing Section

    Details are covered

     Advanced Digital

    Class

    ! Vector Definition Section

    Vector Initial_State

    set Reset to "0"

    set CS_bar to "0"

    ………...

    ! Vector Execution section

    unit " Reset"

    execute Initial_State

    execute Assert_reset

    ………. 1

    2

    4

    5

9

    10

    12

    13

    3

    6

    8

    11

    NAND GATE

    Input 1Input2Output

    E1001

    E1011

    E1101

    E1110

    Truth Table

    Digital library Digital library (Declaration Section)

    ! 7400

    ! NAND, 2-Input, Quad

    ! revision A.01.00

    combinatorial

    vector cycle 500n

    receive delay 400n

    assign VCC to pins 14

    assign GND to pins 7

    assign E1_Inputs to pins 1,2 assign E2_Inputs to pins 4,5 assign E3_Inputs to pins 9,10 assign E4_Inputs to pins 12,13 assign E1_Output to pins 3 assign E2_Output to pins 6 assign E3_Output to pins 8 assign E4_Output to pins 11 power VCC, GND

    family TTL

    inputs E1_Inputs,E2_Inputs,E3_Inputs,E4_Inputs

    outputs E1_Output,E2_Output,E3_Output,E4_Output

    Digital library Digital library ((Vector Definition Section)

    vector E1_Input_00

    set E1_Inputs to "00"

    set E1_Output to "1"

    end vector

    vector E1_Input_01

    set E1_Inputs to "01"

    set E1_Output to "1"

end vector

    vector E1_Input_10

    set E1_Inputs to "10"

    set E1_Output to "1"

    end vector

    vector E1_Input_11

    set E1_Inputs to "11"

    set E1_Output to "0"

    end vector

    ………

    vector E4_Input_00

    set E4_Inputs to "00"

    set E4_Output to "1"

    end vector

    vector E4_Input_01

    set E4_Inputs to "01"

    set E4_Output to "1"

    end vector

    vector E4_Input_10

    set E4_Inputs to "10"

    set E4_Output to "1"

    end vector

    vector E4_Input_11

    set E4_Inputs to "11"

    set E4_Output to "0"

    end vector

    "0"set a logic low on the node. "1"set a logic high on the node. "K"keep the previous state. "T"toggle from the previous state.

    "Z"set the device to a high impedance state.

    "X"don't care this receiver. Digital library Digital library ((unit section)

    unit "Element number 1" execute E1_Input_11

    execute E1_Input_01

    execute E1_Input_00

    execute E1_Input_10

    end unit

    unit "Element number 2" execute E2_Input_11

    execute E2_Input_01

    execute E2_Input_00

    execute E2_Input_10

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