EMI Rule Check
1.1 Check the issues caused by return path 1. Traces crossing over power and ground planes 2. Discontinuity of return current path 1.2 Check the issues caused by signal 3. Trace length 4. Number of via 5. Traces near plane edge 6. Estimation of radiated electric field 7. SG traces 8. Filters on a trace connected to a connector 9. Differential Pair 1.3 Check the issues caused by Power 10. Distance between grounding vias of SG traces 11. Grounding vias along to ground-plane edge 12. Decoupling capacitor placement
RETURN PATH) 1.1. vcc planes) 1.2. GND
(CHECK THE ISSUES CAUSED BY (Trace crossing over power and ground
(discontinuity of return current path)
2.1. 2.2. 2.3. 2.4. 2.5. 2.6. 2.7.
(CHECK THE ISSUES CAUSED BY SIGNAL)
(Trace lenth) (Number of via) (Trace near plane edge) (Estimation of radiated electric field) (SG Trace) (Filters on a trace connected to a connector) (Differential Pair)
3.1. 3.2. 3.3.
(CHECK THE ISSUES CAUSED BY POWER)
(Distance between grounding vias of SG traces) (Grounding vias along to ground-plane edge) (Decoupling capacitor placement)
PCB Design Flow Up To Now
Problem causes at Evaluation Stage
No care No care about Art about Art Work Work PCB Pattern Design A handful of A handful of technical people technical people work for EMC work for EMC Prototype Evaluation
Limited countermeasures after completion of Design/prototype
Manufacture Of PCB
Reiteration Turn back as Problem causes Long TAT
Improvement of PCB Design Flow
Execute fundamental counter measures and Solve all problems at
Design PCB Pattern Design Prototype Evaluation
Manufacture Of PCB
Solve the problem at design step
All steps can be proceed smoothly
Complete Design without any reiteration
(1) Trace length Long wires -> increases current Loop area
Excess total Length of wires per net
(2) Numbers of Via-holes Vias cause excitation point of resonance,
disorder of signal wave
Exceed number of Via per net
(3)Traces near plane edges Wires at the edge of Board -> disorder
range of the Discontinuities of return current path GND Plane
Wires exists at the edge of plane
(4) Traces crossing over GV planes Trace crossing over power and
ground plane -> discontinuity of return path
Trace cross over GV planes
Signal layer Ground plane Power plane Signal layer
(5)Discontinuities of return current path
Discontinuities of return current path -> Increase current loop area
SG pattern leads to Discontinuities
of return current path Discontinuities return current path occurs by across the slit SG Trace Via
(6) SG trace check No SG Pattern -> unable to reinforce return current path SG trace
No SG trace
(7)Estimation of radiated electric field
Differential-mode radiation is calculated using simple equivalent circuit.
Rdump Z0, length I(f)
Estimate volume of radiation electric field of common mode based on differential mode
Large radiation (DM: Large CM: Large)
Medium radiation (DM: Large CM: Medium) Small radiation (DM: Small CM:Medium) Total radiation =Differential mode radiation + Common mode radiation
(8)Distance between grounding vias of SG traces
Inadequate grounding via interval -> No fulfill SG Pattern function.
Interval of grounding vias is too long.
There is no via at the end
(9) Grounding vias along ground plane edge
No Via on circumference of the plane -> Decrease Performance of return current path No Via at the corner of the plane
Exceed distance between Vias Signal GND Plane
(10) Filters on a trace connected to a connector Incomplete filters -> noise occur at connectors Connector
Over distance to the filter Filter
(11) Differential pair check Differential pair suppose to be low EMI, causes many occasion of EMI
Check for differential length, parallel, altered Impedance of wires
-> Available for verification of critical pair wire design
(b1)Exceed Max (b2)Between Min/Max
(12) Decoupling Capacitor Incomplete Decoupling Capacitor ->
Excitation Point on Plane
Over distance to Capacitor
Too short distance to plane No Decoupling Capacitor
Power plane resonance analysis Power plane
Parasitic resistance/Inductance of Capacitor + Parasitic
resistance/Inductance of traces/vias
Interface to Layout CAD systems
Zuken Cadence Mentor Graphics Visula Allegro
PADS Layout ASCII
EMIStream BD Interface
EMIStream PADS Layout Interface
Solution of EMIStream
Easy to use.
Don??t need parameter (Including NEC know how)
High Speed checking.
Checking time is 60 seconds average. You can check anytime and no
stress builds up!!
Decrease Turn around time.
Must take measures EMI at design process.
Decrease EMI engineer??s job
Many EMI problems are able to be solved at design stage.
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