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     Ultra-Low Capacitance TVS Diode Array

     General Description

     The AOZ8005 is a transient voltage suppressor array designed to protect high speed data lines such as HDMI and Gigabit Ethernet from damaging ESD events. This device incorporates eight surge rated, low capacitance steering diodes and a TVS in a single package. During transient conditions, the steering diodes direct the transient to either the positive side of the power supply line or to ground. The AOZ8005 provides a typical line to line capacitance of 0.47pF and low insertion loss up to 2GHz providing greater signal integrity making it ideally suited for HDMI 1.3 applications, such as Digital TVs, DVD players, set-top boxes and mobile computing devices. The AOZ8005 comes in RoHS compliant, tiny SOT-23-6 and MSOP-10 packages and is rated -40?ãC to +85?ãC junction temperature range. The MSOP package features a ?ow through layout design.



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     ESD protection for high-speed data lines: ?C IEC 61000-4-2, level 4 (ESD) immunity test ?C ?À15kV (air discharge) and ?À8kV (contact discharge) ?C Human Body Model (HBM) ?À15kV Array of surge rated diodes with internal TVS diode Small package saves board space Protects four I/O lines Low capacitance between I/O lines: 0.47pF Low clamping voltage Low operating voltage: 5.0V


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     HDMI ports Monitors and ?at panel displays Set-top box USB 2.0 power and data line protection Video graphics cards Digital Video Interface (DVI) 10/100/1000 Ethernet Notebook computers

     Typical Application

     AOZ8005 AOZ8005

     TX2+ TX2TX1+ TX1HDMI Transmitter TX0+ TX0CLK+ CLKConnector Connector

     RX2+ RX2RX1+ RX1RX0+ RX0CLK+ CLK-

     HDMI Receiver



     Figure 1. HDMI Ports

     Rev. 1.8 December 2007


     Page 1 of 14


     Ordering Information

     Part Number

     AOZ8005CI AOZ8005FI

     Ambient Temperature Range

     -40?ãC to +85?ãC


     SOT-23-6 MSOP-10


     RoHS Compliant

     All AOS Products are offering in packaging with Pb-free plating and

    compliant to RoHS standards. Please visit

    www.aosmd.com/web/quality/rohs_compliant.jsp for additional


     Pin Con?guration


     1 6


     CH1 CH2

     1 2 3 4 5

     10 9 8 7 6






     VN CH3







     (Top View)


     (Top View)

     Absolute Maximum Ratings

     Exceeding the Absolute Maximum ratings may damage the device.


     Storage Temperature (TS) ESD Rating per IEC61000-4-2, ESD Rating

    per IEC61000-4-2, contact(1) air(1) ?À8kV ?À15kV ?À15kV


     -65?ãC to +150?ãC

     ESD Rating per Human Body Model(2)

     Notes: 1. IEC 61000-4-2 discharge with CDischarge = 150pF, RDischarge = 330?. 2. Human Body Discharge per MIL-STD-883, Method 3015 CDischarge = 100pF, RDischarge = 1.5k?.

     Maximum Operating Ratings


     Junction Temperature (TJ)


     -40?ãC to +125?ãC

     Rev. 1.8 December 2007


     Page 2 of 14


     Electrical Characteristics

     TA = 25?ãC unless otherwise speci?ed. Speci?cations in BOLD indicate a temperature range of -40?ãC to +85?ãC.




     Reverse Working Voltage Reverse Breakdown Voltage Reverse Leakage Current Diode Forward Voltage Channel Clamp Voltage Positive Transients Negative Transient Channel Clamp Voltage Positive Transients Negative Transient Channel Clamp Voltage Positive Transients Negative Transient Between VP


     and VN(3) and VN(4)






     V V

     IT = 1mA, between VP IF = 15mA

     6.6 1 0.70 Ground(5) 9.18 -1.85 0.85 1

     VRWM = 5V, between VP and VN IPP = 1A, tp = 100ns, any I/O pin to

     ?ÌA V V V V V V V pF pF pF pF pF

     IPP = 5A, tp = 100ns, any I/O pin to Ground(5) 11 -3.40 IPP = 12A, tp = 100ns, any I/O pin to Ground(5) 14.2 -6.30 VR = 0V, f = 1MHz, any I/O pin to Ground(6) VR = 0V, f = 1MHz, between I/O pins(6) VP = 3.3V, VR = 1.65V, f = 1MHz, any I/O pin to Ground VP = 5.0V, VR = 2.5V, f = 1MHz, any I/O pins to ground 1.0 0.47 0.75 0.75 1.05 0.50 0.85 0.85 0.03


     Channel Input Capacitance


     Channel Input Capacitance Matching

     VR = 0V, f = 1MHz, between I/O pins

     Notes: 3. The working peak reverse voltage, VRWM, should be equal to or greater than the DC or continuous peak operating voltage level. 4. VBR is measured at the pulse test current IT. 5. Measurements performed using a 100ns Transmission Line Pulse (TLP) system. 6. Measure performed with no external capacitor on VP.

     Rev. 1.8 December 2007


     Page 3 of 14


     Typical Operating Characteristics

     Clamping Voltage vs. Peak Pulse Current

     (tperiod = 100ns, tr = 1ns) 15 Clamping Voltage, Vcl (V) 14 Forward Voltage (V) 13 12 11 10 9 8 7 6 5 0 2 4 6 8 Peak Pulse Current (A) 10 12 7 6 5 4 3 2 1 0 0 2 4 6 8 10 Forward Current (A) 12 14

     Forward Voltage vs. Forward Current

     (tperiod = 100ns, tr = 1ns)

     Capacitance vs. Reverse Voltage

     1.5 21 18 15 12 9 6 3 0 -3 -6 -9 -12 -15 -18 -21 1

     I/O ?C Gnd Insertion Loss vs. Frequency

     VP = Floating VP = 3.3V

     VP = Floating 1 VP = 3.3V 0.5

     0 0 0.5 1 2 3 1.5 2.5 3.5 Reverse Volts, Vr (V) 4 4.5 5

     Insertion Loss (dB)

     Capacitance (pF)


     100 Frequency (MHz)


     ESD Response (8kV Contact per IEC61000-4-2) Insertion Loss vs. Frequency

     3 0 S21 (dB) -3 -6 -9 -12 1 10 100 Frequency (MHz) 1,000 10,000 VP = Floating -3dB 2,340MHz

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     Page 4 of 14


     Application Information

     The AOZ8005 TVS is design to protect four high speed data lines from ESD and transient over-voltage by clamping them to a ?xed voltage. When the voltages on the protected lines exceed the limit, the internal steering diode are forward bias will conduct the harmful transient away

    from the sensitive circuitry. As system frequency increase, printed circuit board layout becomes more complex. A successful high speed board must integrate the device and traces while avoiding signal transmission problems associated with HDMI data speed. transient over-voltages by clamping them to a ?xed reference. The low inductance and construction minimizes voltage overshoot during high current surges. When the voltage on the protected line exceeds the reference voltage the internal steering diodes are forward biased, conducting the transient current away from the sensitive circuitry. The AOZ8005 is designed for the ease of PCB layout by allowing the traces to run underneath the device. The pinout of the AOZ8005 is design to simply drop onto the IO lines of a High De?nition Multimedia Interface (HDMI) design without having to divert the signal lines that may add more parasitic inductance. Pins 1, 2, 4 and 5 are connected to the internal TVS devices and pins 6, 7, 9 and 10 are no connects. The no connects was done so the package can be securely soldered onto the PCB surface. See Figure 2.

     CH 1 CH 2 VN CH 3 CH 4 CH 1 CH 2 VP CH 3 CH 4

     High Speed HDMI PCB Layout Guidelines

     Printed circuit board layout is the key to achieving the highest level of surge immunity on power and data lines. The location of the protection devices on the PCB is the simplest and most important design rule to follow. The AOZ8005 devices should be located as close as possible to the noise source. The placement of the AOZ8005 devices should be used on all data and power lines that enter or exit the PCB at the I/O connector. In most systems, surge pulses occur on data and power lines that enter the PCB through the I/O connector. Placing the AOZ8005 devices as close as possible to the noise source ensures that a surge voltage will be clamped before the pulse can be coupled into adjacent PCB traces. In addition, the PCB should use the shortest possible traces. A short trace length equates to low impedance, which ensures that the surge energy will be dissipated by the AOZ8005 device. Long signal traces will act as antennas to receive energy from ?elds that are produced by the ESD pulse. By keeping line lengths as short as possible, the ef?ciency of the line to act as an antenna for ESD related ?elds is reduced. Minimize interconnecting line lengths by placing devices with the most interconnect as close together as possible. The protection circuits should shunt the surge voltage to either the reference or chassis ground. Shunting the surge voltage directly to the IC??s signal ground can cause ground bounce. The clamping performance of TVS diodes on a single ground PCB can be improved by minimizing the impedance with relatively short and wide ground traces. The PCB layout and IC package parasitic inductances can cause signi?cant overshoot to the TVS??s clamping voltage. The inductance of the PCB can be reduced by using short trace lengths and multiple layers with separate ground and power

    planes. One effective method to minimize loop problems is to incorporate a ground plane in the PCB design. The AOZ8005 ultra-low capacitance TVS is designed to protect four high speed data transmission lines from

     Figure 2. Flow through Layout for two Line Pair

     It is crucial that the layout is successful for a HDMI design PCB board. Some of the problems associated with high speed design are matching impedance of the traces and to minimize the crosstalk between parallel traces. This application note is to provide you as much information to successfully design a high speed PCB using Alpha & Omega devices. The HDMI video signals are transmitted on a very high speed pair of traces and any amount of capacitance, inductance or even bends in a trace can cause the impedance of a differential pair to drop as much as 40?. This is not desirable because HDMI ports must maintain a 100? ?À15% on each of the four pairs of its differential lines per HDMI Compliance Test Speci?cations. The HDMI CTS speci?es that the impedance on the differential pair of a receiver must be measured using a Time Domain Re?ectometry method with a pulse rise time of ?Ü200pS. The TDR measurements of the PCB traces allows to locate and model discontinuities cause by the geometrical features of a bend and by the frequencydependant losses of the trace itself. These fast edge rates can contribute to noise and crosstalk, depending on the traces and PCB dielectric construction material.

     Rev. 1.8 December 2007


     Page 5 of 14


     Material selection is another aspect that determines good characteristic impedance in the lines. Different material will give you different results. The dielectric material will have the dielectric constant (?År). Where Q1, Q2 = charges, r = distance between charges (m), F = force(N), ?Å = permittivity of dielectric (F/m). By solving for Zo you can calculate the differential impedance with the equation below.

     ?C 0.96 ? ? h Zdiff = 2 ?Á Zo ? 1 ?C 0.48e ? ? ? D


     Q 1Q 2 F = 2 4?Ð?År

     Zdiff = 100.77


     Each PCB substrate has a different relative dielectric constant. The dielectric constant is the permittivity of a relative that of empty space. Where ?År = dielectric constant, ?Å = permittivity, and ?Åo = permittivity of empty space.

     Adjust the trace width, height, distance between the traces and FR4 thickness to obtain the desired 100? differential impedance. The

    general rule of thumb is to route the traces as short as possible, use differential routing strategies whenever feasible and match the length and bends to each of the differential traces. The graphs below show the differential impedance with varying trace width without the AOZ8005 MSOP-10 package part on it. Each of the graphs and board layout represent changing trace width from 50? to 80? in increment of 10?.

     ?Å ?Å r = ?Åo


     The dielectric constant affects the impedance of a transmission line and can propagate faster in materials that have a lower ?År . The frequency in your design will depend on the material being used. With equation 1 you can determine the type of material to use. If higher frequency is required other board material maybe considered. GETEK is another material that can be used in high speed boards. They have a typical ?År between 3.6 to 4.0. The most common type of dielectric material used for PCB is FR-4. Typical dielectric constant for FR-4 is between 4.0 to 4.5. Most PCB manufacture will be able to give you the exact value of the FR-4 dielectric constant. Once you determined the dielectric constant of the board material you can start to calculate the impedance of each trace. Below are the formulas for a microstrip layout. This impedance is dependant on the width of the microstrip (W) the thickness (t) of the trace and the height (h) of the FR4 material, and (D) trace edge to edge spacing.

     W Trace D W t

     Figure 4. 100? Differential Impedance Max 103?, Min 97?



     Dielectric Material


     Figure 3.

     Typical value of W = 12.6 mil, h = 10mils, D = 10mils, t = 1.4mils and ?År = 4.0 with the equation below for a microstrip impedance yields:

     Figure 5. 120? Differential Impedance Max 110?, Min 102?


     5.98 ?Á h 87 Zo = = ln ? ? ? 0.8W + t ? ?Å r + 1.41 Zo = 61.73?

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     Page 6 of 14



     Zo = 61? Z1 C(TVS)

     Zo = 61?

     Figure 7.

     Z1 K = Z2

     Figure 6. 140? Differential Impedance Max 102?, Min 92?


     Z 0 C TVS K X = ? ? ? ? -? ? -? ? 2 ?Ó K ?C1


     Z0 is the normal 61W differential impedance on the trace. Z1 is the need impedance to compensate for the added C(TVS) K is de?ned as the unloaded impedance of the adjusted trace. X is the length of the trace needed for the compensation.

     Figure 7. 160? Differential Impedance Max 123?, Min 109?

     140 Differentail Impedance (?) 120 100 80 60 40 20 0 50 55 60 65 70 75 80

     Min. Max.

     ?Ó is the propagation delay time required for a signal to travel from one point to another. This value should be less than 200pS. From the above method the designer should layout the boards with a 50? common mode trace. The result should give you approximately 100? differential impedance. Z1 is the impedance that you choose in order to compensate the TVS capacitance. Based on Z1 value, we can get the length of the segment from the above equations. With the value of Z1 = 80?, Zo = 61?, C(TVS) = 0.94 and ?Ó = 180. The X(mils) equates to 580 mils. Page 8 has a series of graph that represent changing width and length of the trace from 50? to 80? in increment of 10? with a MSOP-10 package solder onto the board. As you can observe from the graphs, a small incremental capacitance that is added to the differential lines can signi?cantly decrease the differential impedance. Thus violated the HDMI speci?cation of 100??À15%.

     Common Mode Impedance (?)

     Figure 8. Differential Impedance

     By adding a TVS onto the traces it can have a large effect on the impedance of the line. This addition of a capacitance added to a 100? differential transmission line without any compensation may decrease the impedance as much as 20? or more. Below is a formula to calculate the length for the compensation of C(TVS).

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     Page 7 of 14


     Figure 10. 100? Differential Impedance with AOZ8007 MSOP-10 Package on it Max. 97?, Min. 80?

     Figure 12. 140? Differential Impedance with AOZ8007 MSOP-10 Package on it Max. 102?, Min. 92?

     Figure 11. 120? Differential Impedance with AOZ8007 MSOP-10 Package on it Max. 99?, Min. 86?

     Figure 13. 160? Differential Impedance with AOZ8007 MSOP-10 Package

on it Max. 101?, Min. 95?

     From Figure 13 we are able to get the best result from using all of the equation above. With the value of Z1 = 80?, Z0 = 61?, C(TVS) = 0.94, ?Ó = 180 and from Table 1. The X(mils) equates to 580mils to give the best compensated differential impedance on the traces for the added capacitance from the AOZ8005.

     Table 1. AOZ8005 MSOP-10 HDMI Evaluation Board Speci?cation

     Number of layers Copper Trace Thickness Dielectric Constant ?År Overall Board Thickness Dielectric thickness between top and ground layer 4 1.4 mils 4 62 mils 10 mils

     Rev. 1.8 December 2007


     Page 8 of 14



     This application section discusses ESD protection while maintaining the differential impedance of a HMDI sink device. Since the TVS add capacitance we must design the board to meet the HDMI requirements. This application note is a guideline to calculate and layout the PCB. Different board manufacture and process will ?uctuate and will cause the ?nal board to vary slightly. You must carefully plan out a successful high speed HDMI PCB. Factor such as PCB stack up, ground bounce, crosstalk and signal re?ection can interfere with a signal. The layout, trace routing, board materials and impedance calculation discussed in this application note can help you design a more effective PCB using the AOZ8005 devices.

     100? Differential

     160? Differential

     580 mils

     Figure 14. Recommend Layout for MSOP-10 Package

     100? Differential

     Table 2. AOZ8005 SOT-23-6 Evaluation Board Speci?cations

     Number of layers Copper Trace Thickness Dielectric Constant ?År Overall Board Thickness Dielectric thickness between top and ground layer 4 1.4 mils 4 62 mils 10 mils

     160? Differential

     580 mils Total Distance

     Figure 15. Recommended Layout for SOT-23 Package

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     Package Dimensions, SOT23-6L

     Gauge Plane D e1 c L Seating Plane 0.25mm

     E E1

     ?È1 e b


     A2 .010mm A1

     Dimensions in millimeters


     Symbols A A1 A2 b c D E E1 e e1 L ?È1 Min. 0.90 0.00 0.80 0.30 0.08 2.70 2.50 1.50 Nom. ?ª ?ª 1.10 0.40 0.13 2.90 2.80 1.60 Max. 1.25 0.15 1.20 0.50 0.20 3.10 3.10 1.70

     Dimensions in inches

     Symbols A A1 A2 b c D E E1 e e1 L ?È1 Min. 0.035 0.00 0.031 0.012 0.003 0.106 0.098 0.059 Nom. ?ª ?ª 0.043 0.016 0.005 0.114 0.110 0.063 Max. 0.049 0.006 0.047 0.020 0.008 0.122 0.122 0.067

     2.40 0.80 0.95 0.63

     UNIT: mm

     0.95 BSC 1.90 BSC 0.30 ?ª 0.60 0?ã ?ª 8?ã

     0.037 BSC 0.075 BSC 0.012 ?ª 0.024 0?ã ?ª 8?ã

     Notes: 1. Package body sizes exclude mold flash and gate burrs. Mold flash at the non-lead sides should be less than 5 mils each. 2. Dimension ??L?? is measured in gauge plane. 3. Tolerance ?À0.100mm (4 mil) unless otherwise specified. 4. Followed from JEDEC MO-178C & MO-193C. 6. Controlling dimension is millimeter. Converted inch dimensions are not necessarily exact.

     Rev. 1.8 December 2007


     Page 10 of 14


     Tape and Reel Dimensions, SOT23-6L


     T D1 P2 E1 P1

     E2 B0



     Unit: mm




     Feeding Direction

     D0 1.00 Min. D1 1.50 ?À0.10 E 8.00 ?À0.30 E1 1.75 ?À0.10 E2 3.50 ?À0.05 P0 4.00 ?À0.10 P1 4.00 ?À0.10 P2 2.00 ?À0.05 T 0.25 ?À0.05

     Package SOT-23 (8mm)

     A0 3.15 ?À0.10

     B0 3.20 ?À0.10

     K0 1.40 ?À0.10

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