Memory technology evolution: an overview of system memory technologies
technology brief, 7th edition
Abstract???? 2 Introduction???? 2 Basic DRAM operation ???? 2 DRAM storage density and power consumption ???? 4 Memory access time???? 4 Chipsets and system bus timing???? 4 Memory bus speed???? 5 Burst mode access???? 5 SDRAM technology ???? 6 Bank interleaving ???? 7 Increased bandwidth ???? 7 Registered SDRAM modules ???? 7 DIMM Configurations ???? 8 Single-sided and double-sided DIMMs ???? 8 Single-rank, dual-rank, and quad-rank DIMMs ???? 8 Advanced memory technologies ???? 10 Double Data Rate SDRAM technologies ???? 10 DDR-1 ???? 10 DDR-2 ???? 12 DDR-3 ???? 13 Module naming convention and peak bandwidth ???? 13 Fully-Buffered DIMMs???? 14 Rambus DRAM ???? 16 Importance of using HP-certified memory modules in ProLiant servers ???? 17 Conclusion???? 18 For more information???? 19 Call to action ???? 19
The widening performance gap between processors and memory along with the growth of memoryintensive business applications are driving the need for better memory technologies for servers and workstations. Consequently, there are several memory technologies on the market at any given time. HP evaluates developing memory technologies in terms of price, performance, and backward compatibility and implements the most promising technologies in ProLiant servers. HP is committed to providing customers with the most reliable memory at the lowest possible cost. This paper summarizes the evolution of memory technology and provides an overview of some the newest memory technologies that HP is evaluating for servers and workstations. The purpose is to allay some of the confusion about the performance and benefits of the dynamic random access memory (DRAM) technologies on the market.
Processors use system memory to temporarily store the operating system, mission-critical applications, and the data they use and manipulate. Therefore, the performance of the applications and reliability of the data are intrinsically tied to the speed and bandwidth of the system memory. Over the years, these factors have driven the evolution of system memory from asynchronous DRAM technologies, such as Fast Page Mode (FPM) memory and Extended Data Out (EDO) memory, to high-bandwidth synchronous DRAM (SDRAM) technologies. Yet, system memory bandwidth has not kept pace with improvements in processor
performance, thus creating a ??performance gap.?? Processor performance, which is often equated to the number of transistors in a chip, doubles every couple of years. On the other hand, memory bandwidth doubles roughly every three years. Therefore, if processor and memory performance continue to increase at these rates, the performance gap between them will widen. Why is the processor-memory performance gap important? The processor is forced to idle while it waits for data from system memory. Thus, the performance gap prevents many applications from effectively using the full computing power of modern processors. In an attempt to narrow the performance gap, the industry vigorously pursues the development of new memory technologies. HP works with Joint Electronic Device Engineering Council (JEDEC) memory vendors and chipset developers during memory technology development to ensure that new memory products fulfill customer needs in regards to reliability, cost, and backward compatibility. This paper describes the benefits and drawbacks regarding price, performance, and compatibility of DRAM technologies. Some descriptions are very technical. For readers who are not familiar with memory technology, the paper begins with a description of basic DRAM operation and terminology.
Basic DRAM operation
Before a computer can perform any useful task, it copies applications and data from the hard disk drive to the system memory. Computers use two types of system memory?ªcache memory and main memory. Cache memory consists of very fast static RAM (SRAM) and is usually integrated with the processor. Main memory consists of DRAM chips that can be packaged in a variety of ways on dual inline memory modules (DIMMs) for the notebook, desktop PC, and server markets.
Each DRAM chip contains millions of memory locations, or cells, that are arranged in a matrix of rows and columns (Figure 1). On the periphery of the array of memory cells are transistors that read, amplify, and transfer the data from the memory cells to the memory bus. Each DRAM row, called a page, consists of several DRAM cells. Each DRAM cell on a page contains a capacitor capable of storing an electrical charge for a very short time. A charged cell represents a ??1?? data bit, and an uncharged cell represents a ??0?? data bit. The capacitors discharge over time so they must be recharged, or refreshed, thousands of times per second to maintain the validity of the data. These refresh mechanisms are described later in this section.
Figure 1. Representation of a single DRAM chip on a DIMM
The memory subsystem operates at the memory bus speed. Typically, a DRAM cell is accessed when the memory controller sends electronic address signals that specify the row address and column address of the
target cell. The memory controller sends these signals to the DRAM chip by way of the memory bus. The memory bus consists of two sub-buses: the address/command bus and the data bus. The data bus is a set of lines (traces) that carry the data to and from DRAM. Each trace carries one data bit at a time. The throughput (bandwidth) of the data bus depends on its width (in bits) and its frequency. The data width of a memory bus is usually 64-bits, which means that the bus has 64 traces, each of which transports one bit at a time. Each 64-bit unit of data is called a data word. The address portion of the address/command bus is a set of traces that carry signals identifying the location of data in memory. The command portion of the address/command bus conveys instructions such as read, write, or refresh. When FPM or EDO memory writes data to a particular cell, the location where the data will be written is selected by the memory controller. The memory controller first selects the page by strobing the Row Address onto the address/command bus. It then selects the exact location by strobing the Column Address onto the address/command bus (see Figure 2). These actions are called Row Address Strobe (RAS) and Column Address Strobe (CAS). The Write Enable (WE) signal is activated at the same time as the CAS to specify that a write operation is to be performed. The memory controller then drives the data onto the memory bus. The DRAM devices latch the data and store it into the respective cells. During a DRAM read operation, RAS followed by CAS are driven onto the memory bus. The WE signal is held inactive, indicating a read operation. After a delay called CAS Latency, the DRAM devices drive the data onto the memory bus. While DRAM is being refreshed, it cannot be accessed. If the processor makes a data request while the DRAM is being refreshed, the data will not be available until after the refresh is complete. There
are many mechanisms to refresh DRAM, including RAS only refresh, CAS before RAS (CBR) refresh, and Hidden refresh. CBR, which involves driving CAS active before driving RAS active, is used most often.
Figure 2. Representation of a write operation for FPM or EDO RAM
DRAM storage density and power consumption
The storage capacity (density) of DRAM is inversely proportional to the cell geometry. In other words, storage density increases as cell geometry shrinks. Over the past few years, improvements in DRAM storage density have increased capacity from almost 1 kilobit (Kb) per chip to 2 gigabit (Gb) per chip. In the near future, it is expected that capacity will increase even further to 4 Gb per chip. The industry-standard operating voltage for computer memory components was originally at 5 volts. However, as cell geometries decreased, memory circuitry became smaller and more sensitive. Likewise, the industry-standard operating voltage has decreased. Today, computer
memory components operate at 1.8 volts, which allows them to run faster and consume less power.
Memory access time
The length of time it takes for DRAM to produce the data, from the CAS signal until the data is available on the data bus, is called the memory access time or CAS Latency. Memory access time is measured in billionths of a second (nanoseconds, ns) for asynchronous DRAM. For synchronous DRAM, the time is converted to number of memory bus clocks.
Chipsets and system bus timing
All computer components that execute instructions or transfer data are controlled by a system bus clock. The system chipset controls the speed, or frequency, of the system bus clock and thus regulates the traffic between the processor, main memory, PCI bus, and other peripheral buses. The bus clock is an electronic signal that alternates between two voltages (designated as ??0?? and ??1?? in Figure 3) at a specific frequency. The bus frequency is measured in millions of cycles per second, or megahertz (MHz). During each clock cycle, the voltage signal transitions from "0" to "1" and back to "0". A complete clock cycle is measured from one rising edge to the next rising edge. Data transfer along the memory bus can be triggered on either the rising edge or falling edge of the clock signal.
Figure 3. Representation of a bus clock signal
Over the years, some computer components have gained in speed more than others have. For this reason, the components in a typical server are controlled by different clocks that run at different, but related, speeds. These clocks are created by using various clock multiplier and divider circuits to generate multiple signals based on the main system bus clock. For example, if the main system bus operates at 100 MHz, a divider circuit can generate a PCI bus frequency of 33 MHz (system clock ?Â 3) and a multiplier circuit can generate a processor frequency of 400 MHz (system clock x 4). Computer components that operate in whole multiples of the system clock are termed synchronous because they are ??in sync?? with the system clock. Synchronous components operate more efficiently than components that are not synchronized (asynchronous) with the system bus clock. With asynchronous components, either the rest of the system or the component itself must wait one or more additional clock cycles for data orinstructions due to clock resynchronization. In contrast, synchronized components know on which clock cycle data will be available, thus eliminating these timing delays.
Memory bus speed
The speed of the DRAM is not the same as the true speed (or frequency) of the overall memory subsystem. The memory subsystem operates at the
memory bus speed, which may not be the same frequency (in MHz) as the main system bus clock. The two main factors that control the speed of the memory subsystem are the memory timing and the maximum DRAM speed.
Burst mode access
The original DRAM took approximately six system bus clock cycles for each memory access. During memory access, the RAS and CAS were sent first and then 64 bits of data were transferred through the memory bus. The next sequential address access required a repeat of the RAS-CAS-Data sequence. As a result, most of the overhead occurred while transferring row and column addresses, rather than the data. FPM and EDO improved performance by automatically retrieving data from sequential memory locations on the assumption that they too will be requested. Using this process called burst mode access, four consecutive 64-bit sections of memory are accessed, one after the other, based on the address of the first section. So instead of taking six clock cycles to access each of the last three 64-bit sections, it may take from one to three clock cycles each (see Figure 4). Burst mode access timing is normally stated in the format ??x-y-y-y?? where ??x?? represents the number of clock cycles to read/write the first 64 bits and ??y?? represents the number of clock cycles required for the second, third, and fourth reads/writes. For example, prior to burst mode access, DRAM took up to 24 clock cycles (6-6-6-6) to access four 64-bit memory sections. With burst mode access, three
additional data sections are accessed with every clock cycle after the first access (6-1-1-1) before the memory controller has to send another CAS.
Figure 4. Burst mode access. NOP is a ??No Operation?? instruction.
Clock Command Address Data
Active Row NOP NOP Read Col
Data 64b Data
FPM and EDO DRAMs are controlled asynchronously, that is, without
a memory bus clock. The memory controller determined when to assert signals and when to expect data based on absolute timing. The inefficiencies of transferring data between a synchronous system bus and an asynchronous memory bus resulted in longer latency. Consequently, JEDEC?ªthe electronics industry standards agency for memory devices and modules?ª developed the synchronous DRAM standard to reduce the number of system clock cycles required to read or write data. SDRAM uses a memory bus clock to synchronize the input and output signals on the memory chip. This simplified the memory controller and reduced the latency from CPU to memory. In addition to synchronous operation and burst mode access, SDRAM has other features that accelerate data retrieval and increase memory capacity?ªmultiple memory banks, greater bandwidth, and register logic chips. Figure 5 shows SDRAM DIMMs with two key notches that prevent incorrect insertion and indicate a particular feature of the module.
Figure 5. SDRAM DIMM with two notches
SDRAM divides memory into two to four banks for simultaneous access to more data. This division and simultaneous access is known as interleaving. Using a notebook analogy, two-way interleaving is like dividing each page in a notebook into two parts and having two assistants to each retrieve a different part of the page. Even though each assistant must take a break (be refreshed), breaks are staggered so that at least one assistant is working at all times. Therefore, they retrieve the data much faster than a single assistant could get the same data from one whole page, especially since no data can be accessed when a single assistant takes a break. In other words, while one memory bank is being accessed, the other bank remains ready to be accessed. This allows the processor to initiate a new memory access before the previous access has been completed, resulting in continuous data flow.
The bandwidth capacity of the memory bus increases with its width (in bits) and its frequency (in MHz). By transferring 8 bytes (64 bits) at a time and running at 100 MHz, SDRAM increases memory bandwidth to 800 MB/s, 50 percent more than EDO DRAMs (533 MB/s at 66 MHz).
Registered SDRAM modules
To achieve higher memory subsystem capacity, some DIMMs have register logic chips (registers) that act as a pass-through buffer for address and command signals (Figure 6). Registers prevent the chipset from having to drive the entire arrangement of DRAM chips on each module. Rather, the chipset drives only the loading of the registers on each module. The register on each DIMM re-drives the address and command signals to the appropriate DRAM chip. Simultaneously, a phase lock loop
chip on the registered DIMM generates a second clock signal that runs synchronously with the system bus clock. This prevents the system bus clock signal from having to drive all the DRAM chips, and it allows the addition of more memory modules to the memory bus to increase memory capacity.
Figure 6. Registered DIMMs
Single-sided and double-sided DIMMs Each DRAM chip on a DIMM provides either 4 bits or 8 bits of a 64-bit data word. Chips that provide 4 bits are called x4 (by 4), and chips that provide 8 bits are called x8 (by 8). It takes eight x8 chips or sixteen x4 chips to make a 64-bit word, so at least eight chips are located on one or both sides of a DIMM. However, a standard DIMM has enough room to hold a ninth chip on each side. The ninth chip is used to store 4 bits or 8 bits of Error Correction Code, or ECC (see ??Parity and ECC DIMMs?? sidebar on next page). An ECC DIMM with all nine DRAM chips on one side is called single-sided, and an ECC DIMM with nine DRAM chips on each side is called double-sided (Figure 7). A single-sided x8 ECC DIMM and a double-sided x4 ECC DIMM each create a single block of 72 bits (64 bits plus 8 ECC bits). In both cases, a single chip-select signal from the chipset is used to activate all the chips on the DIMM. In contrast, a double-sided x8 DIMM (bottom illustration) requires two chip-select signals to access two 72-bit blocks on two sets of DRAM chips. Single-rank, dual-rank, and quad-rank DIMMs In addition to single-sided and double-sided configurations, DIMMs are classified as single-rank or dual-rank. A memory rank is defined as an area or block of 64-bits created by using some or all of the DRAM chips on a DIMM. For an ECC DIMM, a memory rank is a block of 72 data bits (64 bits plus 8 ECC bits). A single-rank ECC DIMM (x4 or x8) uses all of its DRAM chips to create a single block of 72 bits, and all the chips are activated by one chip-select signal from the chipset (top two illustrations in Figure 7). A dual-rank ECC DIMM produces two 72-bit blocks from two sets of DRAM chips on the DIMM, requiring two chip-select signals. The chip-select signals are staggered so that both sets of DRAM chips do not contend for the memory bus at the same time. Quad-rank DIMMs with ECC produces four 72-bit blocks from four sets of DRAM chips on the DIMM, requiring four chip-select signals. Like the dual-rank DIMMs, the memory controller staggers the chip-select signals to prevent the four sets of DRAM chips from contending for the memory bus at the same time.
Figure 7. Single-sided and double-sided DDR SDRAM DIMMs and corresponding DIMM rank
Parity and ECC DIMMs The ninth DRAM chip on one side of a DIMM is used to store parity or ECC bits. With parity, the memory controller is capable of detecting single-bit errors, but it is unable to correct any errors. Also, it cannot consistently detect multiple-bit errors. With ECC, the memory controller is capable of detecting and correcting single bit errors and multiple-bit errors that are contiguous. Multiple-bit contiguous errors occur when an entire x4 or x8 chip fails. The chipset (memory controller) is also capable of detecting double-bit errors that are not contiguous. The chipset halts the system and logs an error when uncorrectable errors are detected. Servers use ECC DIMMs to improve availability and reliability.
Memory ranks are not new, but their role has become more critical with the advent of new chipset and memory technologies and growing server memory capacities. Dual-rank DIMMs improve memory density by placing the components of two single-rank DIMMs in the space of one module. The chipset considers each rank as an electrical load on the memory bus. At slower bus speeds, the number of loads does not adversely affect bus signal integrity. However, for faster memory technologies such as DDR2-667, there are a maximum number of ranks that the chipset can drive. For example, if a memory bus on a server has four DIMM slots, the chipset may only be capable of supporting two dual-rank DIMMs or four single rank DIMMs. If two dual-rank DIMMs are installed then, the last two slots must not be populated. To compensate for the reduction in the number of DIMM slots on a bus at higher speeds, modern chipsets employ multiple memory buses. If the total number of ranks in the populated DIMM slots exceeds the maximum number of loads the chipset can support, the server may not boot properly or it may not operate reliably. Some systems check the memory configuration while booting to detect invalid memory bus loading. When an invalid memory configuration is detected, the system stops the boot process, thus avoiding unreliable operation. To prevent this and other memory-related problems, customers should only use HP-certified DIMMs available in the memory option kits for each ProLiant server (see the ??Importance of using HP-certified memory modules in ProLiant servers?? section). Another important difference between single-rank and dual-rank DIMMs is cost. Typically, memory costs increase with DRAM density. For example, the cost of an advanced, high-density DRAM chip is typically much higher (more than 2x) than that of a conventional DRAM chip. Because large capacity single-rank DIMMs are manufactured with higher-density DRAM chips, they typically cost more than dual-rank DIMMs of comparable capacity.
Advanced memory technologies
Despite the performance improvement in the overall system due to use of SDRAM, the growing performance gap between the memory and
processor must be filled by more advanced memory technologies. These technologies, which are described on the following pages, boost the overall performance of systems using the latest high-speed processors (Figure 8).
Figure 8. Peak bandwidth comparison of SDRAM and advanced SDRAM technologies
Double Data Rate SDRAM technologies
Double Data Rate (DDR) SDRAM is advantageous for systems that require higher bandwidth than can be obtained using SDRAM. Basically, DDR SDRAM doubles the transfer rate without increasing the frequency of the memory clock. This section describes three generations of DDR SDRAM technology. DDR-1 To develop the first generation of DDR SDRAM (DDR-1), designers made enhancements to the SDRAM core to increase the data rate. These enhancements include prefetching, double transition clocking, strobe-based data bus, and SSTL_2 low voltage signaling. At 400 MHz, DDR increases memory bandwidth to 3.2 GB/s, which is 400 percent more than original SDRAM. Prefetching In SDRAM, one bit per clock cycle is transferred from the memory cell array to the input/output (I/O) buffer or data queue (DQ). The I/O buffer releases one bit to the bus per pin and clock cycle (on the rising edge of the clock signal). To double the data rate, DDR SDRAM uses a technique called prefetching to transfer two bits from the memory cell array to the I/O buffer in two separate pipelines. Then the I/O buffer releases the bits in the order of the queue on the same output line. This is known as a 2n-prefetch architecture because the two data bits are fetched from the memory cell array before they are released to the bus in a time multiplexed manner.
Double transition clocking Standard DRAM transfers one data bit to the bus on the rising edge of the bus clock signal, while DDR-1 uses both the rising and falling edges of the clock to trigger the data transfer to the bus (Figure 9). This technique, known as double transition clocking, delivers twice the bandwidth of SDRAM without increasing the clock frequency. DDR-1 has theoretical peak data transfer rates of 1.6 and 2.1 GB/s at clock frequencies of 100 MHz and 133 MHz, respectively.
Figure 9. Data transfer rate comparison between SDRAM (with burst mode access) and DDR SDRAM
SSTL_2 low-voltage signaling technology Another difference between SDRAM and DDR-1 is the signaling technology. Instead of using a 3.3-V operating voltage, DDR-1 uses a 2.5-V signaling specification known as Stub Series-Terminated Logic_2 (SSTL_2). This low-voltage signaling results in lower power consumption and improved heat dissipation. Stobe-based data bus SSTL_2 signaling allows DDR-1 to run at faster speeds than traditional SDRAM. In addition, DDR-1 uses a delay-locked
loop (one for every 16 outputs) to provide a data strobe signal as data becomes valid on the SDRAM pins. The memory controller uses the data strobe signal to locate data more accurately and resynchronize incoming data from different DIMMs. DDR-1 operates at transfer rates of 400 Mb/s, or 3.2 GB/s. Although the data bus is capable of running at these speeds, the command bus cannot. Tight system timing requirements were alleviated on the data bus by using strobes. However, the command bus does not use a strobe and must still meet setup times to a synchronous clock. Thus, at a data rate of 400 Mb/s, the command bus must operate at 200 MHz.
DDR-1 DIMMs DDR-1 DIMMs require 184 pins instead of the 168 pins used by standard SDRAM DIMMs. DDR-1 is versatile enough to be used in desktop PCs or servers. To vary the cost of DDR-1 DIMMs for these different markets, memory manufacturers provide unbuffered and registered versions. Unbuffered DDR-1 DIMMs place the load of all the DDR modules on the system memory bus, but they can be used in systems that do not require high memory capacity. Registered DDR-1 DIMMs (Figure 10) place only one load per DIMM on the memory bus, regardless of how many SDRAM devices are on the module. Therefore, they are best suited for servers with very high memory capacities.
Figure 10. The 184-pin DRR-1 Registered DIMM. The DDR-1 DIMM has one notch instead of the two notches found on SDRAM DIMMs.
Backward compatibility Because of their different data strobes, voltage levels, and signaling technologies, it is not possible to mix SDRAM and DDR-1 DIMMS within the same memory subsystem. DDR-2 DDR-2 SDRAM is the second generation of DDR SDRAM. It offers data rates of up to 6.4 GB/s, lower power consumption, and improvements in packaging. At 400 MHz and 800 Mb/s, DDR-2 increases memory bandwidth to 6.4 GB/s, which is 800 percent more than original SDRAM. DDR-2 SDRAM achieves this higher level of performance and lower power consumption through faster clocks, 1.8-V operation and signaling, and simplification of the command set. The 240-pin connector on DDR-2 is needed to accommodate differential strobes signals (Figure 11).
Figure 11. The DDR-2 DIMM has a 240-pin interface
DDR-3 DDR-3, the third-generation of DDR SDRAM technology, will make further improvements in bandwidth and power consumption. Manufacturers of DDR-3 will initially use 90 nm fabrication technology and move toward 70 nm as production volumes increase. DDR-3 will operate at clock rates from 400 MHz to 800 MHz with theoretical peak bandwidths ranging from 6.40 GB/s to 12.8 GB/s. DDR-3 is expected to reduce power consumption by up to 30% compared to a DDR-2 DIMM operating at the same speed. DDR-3 DIMMs are expected to use the same 240-pin connector as DDR2 DIMMs,