TXT

ALC203-datasheet

By Robin Stevens,2014-05-27 15:05
12 views 0
ALC203-datasheet

     ??ÎÄÓÉwzjsky006??Ï×

    pdfÎĵµ?ÉÄÜÔÚWAP?Ëä?ÀÀÌåÑé???Ñ????ÒéÄúÓÅÏÈÑ?ÔñTXT???òÏÂÔØÔ?ÎÄ?þµ????ú?é????

     ALC203

     REALTEK SEMICONDUCTOR INC. ALC203 APPLICATION NOTES

     0. Revision History ???? 1 1. Introduction???? 1 2. Mixer Block Diagram ???? 2 3. Saving 24.576MHz Crystal???? 3 4. Output Amplifier at HP-OUT???? 5 5. General Purpose I/O (GPIO) ???? 5 6. Smart GPIO Volume Control???? 5 7. Stereo MIC Input ???? 6 8. S/PDIF-In Function ???? 7 9. Pin Assignments ???? 7 10. Complete Application Circuits???? 7 11. Regulator Selection ???? 8 12. S/PDIF IO Layout Guide???? 9 13. Jack Sense????11 14. Universal Audio Jack ????? 12

     0. Revision History

     Version 0.2: (1) Add Jack Sense circuit (2) Add Universal Audio Jack ? circuit (3) Add Smart GPIO Volume Control ? circuit (4) Add application circuit for motherboard

     1. Introduction

     The ALC203 has a 20-bit stereo DAC and 18-bit stereo ADC, full duplex AC'97 2.3 compatible audio CODEC designed for PC multimedia systems, including host/soft audio and AMR/CNR based designs. The ALC203 incorporates proprietary converter technology to achieve a high SNR, greater than 95 dB. The ALC203 AC'97 CODEC supports independent variable sampling rates and built-in 3D effects. This document contains some notes on application circuits for the ALC203. This guide is intended for the Realtek customer who will be designing a hardware system around the Realtek ALC203 chip. Using this guide, the following goals can be achieved: (1) Create a noise-free, power stable environment that is suitable for the ALC203. (2) Reduce the possibility of EMI and EMC and their influence to the chip. (3) Simplify the task of routing signal traces, so as to make a better circuit for the ALC203. All information provided in this guide has been tested by Realtek systems engineers to be accurate and directly applicable to proper system designs using ALC203.

     2003/2/20

     1

     Rev.0.2

     2003/2/20

     RESET# MX18 MX0A MX0C MX0E 3D 1 0* MX02 Master Volume

     Yes No Yes No

     DAC output AMP HP-OUT

     PC-BEEP

     MX04 HeadPhone Volume

     PHONE MIC1

     MIC2 MX10 MX12 MX14 MX16 Boost Mono Volume MX06

     1 0*

     0* 1

     Boost

     LINE-OUT

     2. Mixer Block Diagram

     LINE-IN

     CD-IN

     VIDEO-IN AUX-IN

     RESET#

     MONO-OUT

     The Mixer Block Diagram shows the analog data path, and its control

    mixers. The ALC203 supports flexible analog paths to fit different applications.

     Analog data path

     M U X MX1A Record Gain MX1E Record Gain MX1C stereo mix mono mix phone mic-L mic-R line CD video aux left channel /2 right channel 1* 0

     2

     Boost

     to ADC

     ALC203

     MIC ADC

     mono analog stereo analog

     * : default setting

     ALC203

     Rev.0.2

     ALC203

     3. Saving 24.576MHz Crystal

     The ALC203 has a built in 14.318MHz to 24.576MHz phase-lock-loop clock generator. The 14.318MHz frequency from the clock generator can

    be used as the clock source for the ALC203 by pulling XTLSEL (pin-46)

    low.

     Float XTLSEL when 24.576MHz crystal is used

     Pull-low XTLSEL if External 14.318MHz is used

     2003/2/20

     3

     Rev.0.2

     ALC203

     Pull-low XTLSEL if External 14.318MHz crystal is used

     2003/2/20

     4

     Rev.0.2

     ALC203

     4. Output Amplifier at HP-OUT

     The ALC203 embeds 50mW@20? amplifiers @ HP-out and Aux-in as HP-out to drive the headphones, saving external earphone driving circuitry.

     Standard AC97 Requires External Amplifier

     ALC203 Has Embedded Headphone Amplifier

     5. General Purpose I/O (GPIO)

     ALC203 supports 2 GPIO pins for general input-output applications. GPIO0 is at pin43 and GPIO1 is at pin44. Both GPIO0 and GPIO1 can be separately programmed as input or output.

     6. Smart GPIO Volume Control?

     ALC203 supports Smart GPIO Volume Control ? which is designed for N?éD manufacturer. With this circuit, manufacturers can implement volume control by button, and end users can experience one-shot volume up/down or continuously pressing volume up/down

     +3.3VDD

     GPIO Volume Control

     R53 4.7K R55 R56 Vol-Mute Vol-Down Vol-Up 0 0 GPIO1 GPIO0

     R54 4.7K

     Smart GPIO Volume Control

     2003/2/20

     5

     Rev.0.2

     ALC203

     7. Stereo MIC Input

     ALC203 supports 2 microphone inputs, MIC1 (pin21) and MIC2 (pin22). MIC1 and MIC2 can be implemented as stereo microphone input. Or either microphone input can also be implemented individually.

     Implementation of Stereo MIC-in For the phone jack in the front panel, following INTEL??s ??Front Panel IO Connectivity Design Guide V1.0?? specifications, MIC-in phone jack in the front panel is implemented as in the diagram below.

     Implementation of MIC-in in front panel

     J14 AUD-MIC AUD-MIC-BIAS AUD-OUT-R AUD-OUT-L 1 3 5 7 9 2 4 6 8 10 +5VA AUD-RET-R AUD-RET-L

     Front Panel Connector

     Implementation of MIC-in in front panel connector

     2003/2/20

     6

     Rev.0.2

     ALC203

     8. S/PDIF-In Function

     ALC203 support the S/PDIF-In function. The frequency of the S/PDIF signal is about 1.5MHz~6MHz. Therefore, to prevent cross-talk interference from S/PDIF output, do not layout S/PDIF input and S/PDIF

    output traces in a parallel configuration. It is recommended to maintain double width or ground between S/PDIF input and S/PDIF output traces.

     9. Pin Assignments

     LINE-OUT-R LINE-OUT-L VAUX VREFOUT2 DCVOL NC AFILT2 AFILT1 VREFOUT VREF AVSS1 AVDD1 MONO-OUT/VREFOUT3 AVDD2 HP-OUT-L NC HP-OUT-R AVSS2 GPIO0 GPIO1 ID0# XTLSEL SPDIFI/EAPD SPDIFO

     36 35 34 33 32 31 30 29 28 27 26 25 37 38 39 40 41 42 43 44 45 46 47 48

     ALC203

     1 2 3 4 5 6 7 8 9 10 11 12

     24 23 22 21 20 19 18 17 16 15 14 13

     LINE-IN-R LINE-IN-L MIC2 MIC1 CD-R CD-GND CD-L JD1 JD2 AUX-R AUX-L PHONE

     10. Complete Application Circuits

     The application circuits are contained in a separate file. Please refer to the file titled ??ALC203_Demo_Circuit_Ver_xx.PDF?? for the schematics for those circuits.

     2003/2/20

     DVDD1 XTL-IN XTL-OUT DVSS1 SDATA-OUT BIT-CLK DVSS2 SDATA-IN DVDD2 SYNC RESET# PC-BEEP

     7

     Rev.0.2

     ALC203

     11. Regulator Selection

     The ALC203 has built in amplifiers. It normally consumes 60mA from +5V AVDD when driving active powered speakers. If the ALC203 drives earphones with 16ohm load on both amplifiers, ALC203 will consume more than 100mA power from the +5V regulator when playing a testing full swing sine wave. To prevent the power regulator from overheating, it is recommended to use a +5V regulator with internal thermal overload protection and at least 200mA output current capability. For example the LM7805CT can be used. If only a 78L05 is used to supply 100mA output current, a 20? resister should be placed in the path of HP-out or Aux-in as HP-out to limit current consumption. This will protect the 78L05 from damage.

     Serial resistor on output path to limit current The following table shows the maximum current consumed from AVDD under various loads. These test values are measured by a 2-channel DAC playing a full-scale sinusoidal wave (1KHz, 44.1KHz sampling rate) on HP-out. Powered Speaker 58 mA 58 mA 20 ? Earphone 97 mA 81 mA 16 ? Earphone 110 mA 88 mA 8? passive speaker 141 mA 94 mA

     R13, R15 = 0 ohm R13, R15 = 20 ohm

     Playing a full scale sinusoidal wave, power consumed from +5V AVDD

     2003/2/20

     8

     Rev.0.2

     ALC203

     12. S/PDIF IO Layout Guide

     Crosstalk is an undesirable feature with S/PDIF signals. It causes a disturbance between S/PDIF-IN and S/PDIF-OUT signals. Mutual coupling mechanisms will be formed if S/PDIF-IN and S/PDIF-OUT are parallel, the mutual capacitance and mutual inductance between traces have capacitive and inductive coupling of electromagnetic field generated by S/PDIF-OUT. Figure 12-1 indicates the coupling energy from S/PDIF-OUT may interfere S/PDIF-IN operation.

     VCC3.3 100K 0.01uF 74HC04 3.3V 100K 0V S/PDIF-IN S/PDIF-OUT

     Cross talk

     3.3V 0V

     Long parallel run lines is not guarded by Ground will induce Crosstalk

     Figure 12-1 Crosstalk between S/PDIF-IN and S/PDIF-OUT traces Design and layout rules listed here are useful to prevent crosstalk. 1.Minimize physical distance between IO connector (or header) and ALC203. 2.Avoid routing of S/PDIF-IN trace parallel to S/PDIF-OUT. Figure 12-2 shows an approximate equation to minimize crosstalk, distance (H) with reference plane must be minimized, and distance (D) between traces must be maximized. (Refer to ??High Speed Digital Design??. Johnson, H. W., and M. Graham. 1993. Englewood Cliffs, NJ: Prentice Hall) 3.S/PDIF-IN and S/PDIF-OUT signals are separated by ground traces will reduce crosstalk. (Figure 12-3) 4.A simple rule to minimize coupling between traces is the 3-W rule. The distance separation between centerline of traces must be three times the width of a single trace. (Figure 12-4)

     D Trace1 H

     ground plane

     Trace2 H

     Crosstalk = 1+(

     1 D 2 ) H

     Figure 12-2 Approximate equation to estimate crosstalk

     signal 4

     signal 3

     signal 2

     signal 1 Crosstalk > 5%

     ground plane (Front View) Figure 12-3a Traces without separation have significant crosstalk 2003/2/20 9 Rev.0.2

     ALC203

     ground signal 2 ground signal 1 Crosstalk < 1-2% ground plane (Front View)

     Figure 12-3b Traces separated by ground can reduce crosstalk

     Signal is guarded by ground

     ground trace

     W=12 mils

     S/PDIF-IN trace ground trace S/PDIF-OUT trace (Top View) Figure 12-4 The 3-W rule to minimize coupling

     > 3W

     Additional to above layout rules, the 3-W rule represents the approximate only 70% flux boundary, 10-W should be used to get approximate 98% boundary. (Refer to ??EMC and the Printed Circuit Board??, Mark I. MONTROSE) However, it may be not easy to separate traces with 10-W distance, Figure 12-5 is 5-W (W=12 mils) separations adapted on Realtek??s demo board.

     VCC3.3 100K

     F version

     1.41V

     0.01uF 75K

     or

     VCC3.3 100K 0V 0.01uF 100K 74HC04

     E/F version

     1.65V

     Crosstalk is almost removed

     5W

     Seperated by ground to remove Crosstalk

     S/PDIF-IN S/PDIF-OUT

     3.3V 0V

     Figure 12-5 The suggested layout on Realtek??s demo board

     2003/2/20

     10

     Rev.0.2

     ALC203

     13. Jack Sense

     ALC203 supports AC??97 2.3 ??Jack Sensing and reporting of connected devices?? features on Line-out, Line-in and Mic-in. With this feature, end users could easily get the phone jacks?? status when plugging devices into. However, motherboard manufactures don??t need to change too much in the circuit design. Only need to attach one resistor parallel with filter capacitor on Vrefout, shown as below. And do nothing to Line-out and Line-in for jack sensing.

     Circuit modification of Mic-in Jack Sensing implementation Notice: the resistor R57 is used to fine tune jack sense, so the value may range from 6.8k to 8.2k

     2003/2/20

     11

     Rev.0.2

     ALC203

     14. Universal Audio Jack?

     ALC203 supports a proprietary technology ??Universal Audio Jack?? which bases on AC??97 2.3 ??Jack Sensing and reporting connected device?? concepts and provides more intelligent way to sense the devices plugged into phone jack. ALC203 has 2 sets of UAJ, which are UAJ1 on 39/41 (HP-out) accompanied with JD1 (pin17) and Vrefout3 (pin13), and UAJ2 on 14/15 (Aux-in) accompanied with JD2 (pin16) and Vrefout2 (pin32). Those JDs and Vrefout2/3 are dedicated to each UAJ set, so be careful not to erroneously connect. To implement UAJ, motherboard manufactures need do some modifications on the circuit design. Illustrations of UAJ implemented on the front panel and pin assignment modification of front panel header are shown below.

     UAJ2 on front panel

     UAJ1 on front panel

     Front panel header pin assignment Notice: *UAJ1: pin39,41 (HP-out), pin13 (Vrefout3/Mono-out) and pin17 (JD1) are used *UAJ2: pin14,15 (Aux-in), pin32 (Vrefout2) and pin16 (JD2) are used

     2003/2/20

     12

     Rev.0.2

     ALC203

     Realtek Semiconductor Inc.

     Headquarters 1F, No. 2, Industry East Road IX, Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C. Tel : 886-3-5780211 Fax : 886-3-5774713 WWW: www.realtek.com.tw Email: pctech@realtek.com.tw

     2003/2/20

     13

     Rev.0.2

??TXTÓÉ??ÎÄ?â????ÏÂÔØ:http://www.mozhua.net/wenkubao

Report this document

For any questions or suggestions please email
cust-service@docsford.com