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s5pv210_section_02_system

By Ralph Long,2014-05-27 14:59
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s5pv210_section_02_system

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     Section 2

     SYSTEM

     Table of Contents

     1 Chip ID????1-1

     1.1 Overview of CHIP ID???? 1-1 1.2 Register Description???? 1-2 1.2.1 Register Map ???? 1-2

     2

     General Purpose Input/ Output ????2-1

     2.1 Overview ???? 2-1 2.1.1 Features???? 2-2 2.1.2 Input/ Output Configuration ???? 2-2 2.1.3 S5PV210 Input/ Output Types???? 2-2 2.1.4 IO Driver strength ???? 2-3 2.1.5 Input/ Output Description???? 2-7 2.2 Register Description???? 2-24 2.2.1 Register Map ???? 2-24 2.2.2 Port Group GPA0 Control Register ???? 2-42 2.2.3 Port Group GPA1 Control Register ???? 2-44 2.2.4 Port Group GPB Control Register ???? 2-46 2.2.5 Port Group GPC0 Control Register ???? 2-48 2.2.6 Port Group GPC1 Control Register ???? 2-50 2.2.7 Port Group GPD0 Control Register ???? 2-52 2.2.8 Port Group GPD1 Control Register ???? 2-54 2.2.9 Port Group GPE0 Control Register ???? 2-56 2.2.10 Port Group GPE1 Control Register ???? 2-58 2.2.11 Port Group GPF0 Control Register???? 2-60 2.2.12 Port Group GPF1 Control Register???? 2-63 2.2.13 Port Group GPF2 Control Register???? 2-66 2.2.14 Port Group GPF3 Control Register???? 2-69 2.2.15 Port Group GPG0 Control Register ???? 2-71 2.2.16 Port Group GPG1 Control Register ???? 2-73 2.2.17 Port Group GPG2 Control Register ???? 2-75 2.2.18 Port Group GPG3 Control Register ???? 2-77 2.2.19 Port Group GPI Control Register???? 2-79 2.2.20 Port Group GPJ0 Control Register ???? 2-81 2.2.21 Port Group GPJ1 Control Register ???? 2-84 2.2.22 Port Group GPJ2 Control Register ???? 2-86 2.2.23 Port Group GPJ3 Control Register ???? 2-89 2.2.24 Port Group GPJ4 Control Register ???? 2-92 2.2.25 Port Group MP0_1 Control Register???? 2-94 2.2.26 Port Group MP0_2 Control Register???? 2-96 2.2.27 Port Group MP0_3 Control Register???? 2-98 2.2.28 Port Group MP0_4 Control Register???? 2-101 2.2.29 Port Group MP0_5 Control Register???? 2-103 2.2.30 Port Group MP0_6 Control Register???? 2-105 2.2.31 Port Group MP0_7 Control Register???? 2-107 2.2.32 Port Group MP1_0 Control Register???? 2-109 2.2.33 Port Group MP1_1 Control Register???? 2-109 2.2.34 Port Group MP1_2 Control Register???? 2-110

     2.2.35 Port Group MP1_3 Control Register???? 2-110 2.2.36 Port Group MP1_4 Control Register???? 2-111 2.2.37 Port Group MP1_5 Control Register???? 2-111 2.2.38 Port Group MP1_6 Control Register???? 2-112 2.2.39 Port Group MP1_7 Control Register???? 2-112 2.2.40 Port Group

    MP1_8 Control Register???? 2-113 2.2.41 Port Group MP2_0 Control Register???? 2-113 2.2.42 Port Group MP2_1 Control Register???? 2-114 2.2.43 Port Group MP2_2 Control Register???? 2-114 2.2.44 Port Group MP2_3 Control Register???? 2-115 2.2.45 Port Group MP2_4 Control Register???? 2-115 2.2.46 Port Group MP2_5 Control Register???? 2-116 2.2.47 Port Group MP2_6 Control Register???? 2-116 2.2.48 Port Group MP2_7 Control Register???? 2-117 2.2.49 Port Group MP2_8 Control Register???? 2-117 2.2.50 Port Group ETC0 Control Register???? 2-118 2.2.51 Port Group ETC1 Control Register???? 2-119 2.2.52 Port Group ETC2 Control Register???? 2-121 2.2.53 Port Group ETC3 is reserved ???? 2-123 2.2.54 Port Group ETC4 ???? 2-123 2.2.55 GPIO Interrupt Control Registers ???? 2-124 2.2.56 Port Group GPH0 Control Register ???? 2-233 2.2.57 Port Group GPH1 Control Register ???? 2-235 2.2.58 Port Group GPH2 Control Register ???? 2-237 2.2.59 Port Group GPH3 Control Register ???? 2-239 2.2.60 External Interrupt Control Registers ???? 2-241 2.2.61 Extern Pin Configuration Registers in Power down Mode ???? 2-261

     3

     Clock Controller ????3-1

     3.1 Clock Domains ???? 3-1 3.2 Clock Declaration ???? 3-2 3.2.1 Clocks from Clock Pads ???? 3-2 3.2.2 Clocks from CMU???? 3-3 3.3 Clock Relationship ???? 3-4 3.3.1 Recommended PLL PMS Value for APLL???? 3-5 3.3.2 Recommended PLL PMS Value for MPLL ???? 3-6 3.3.3 Recommended PLL PMS Value for EPLL???? 3-6 3.3.4 Recommended PLL PMS Value for VPLL???? 3-7 3.4 Clock Generation ???? 3-8 3.5 Clock Configuration Procedure ???? 3-12 3.5.1 Clock Gating ???? 3-12 3.6 Special Clock Description ???? 3-13 3.6.1 Special Clock Table ???? 3-13 3.7 Register Description???? 3-15 3.7.1 Register Map ???? 3-15 3.7.2 PLL Control Registers ???? 3-19 3.7.3 Clock Source Control Registers ???? 3-26 3.7.4 Clock Divider Control Register ???? 3-35 3.7.5 Clock Gating Control Register ???? 3-40 3.7.6 Clock Output Configuration Register ???? 3-52 3.7.7 Clock Divider Status SFRs ???? 3-54 3.7.8 Clock MUX Status SFRs ???? 3-56

     3.7.9 Other SFRs???? 3-58 3.7.10 IEM Control SFRs???? 3-58 3.7.11 Miscellaneous SFRs???? 3-64

     4

     Power Management????4-1

     4.1 Overview of PMU ???? 4-1 4.2 FunctionAL Description of PMU???? 4-2 4.3 System Power Mode???? 4-4 4.3.1 Overview???? 4-4 4.3.2 Normal Mode ???? 4-7 4.3.3 IDLE Mode???? 4-9 4.3.4 DEEP-IDLE Mode???? 4-9 4.3.5 STOP Mode ???? 4-11 4.3.6 DEEP-STOP Mode ???? 4-13 4.3.7 SLEEP Mode ???? 4-14 4.4 System Power Mode Transition ???? 4-16 4.4.1 Transition Entering/ Exiting Condition ???? 4-17 4.5 Cortex-A8 Power Mode???? 4-19 4.5.1 Overview???? 4-19 4.5.2 Cortex-A8 Power Mode Transition ???? 4-19 4.5.3 State Save and Restore ???? 4-22 4.6 Wakeup Sources???? 4-23 4.6.1

    External Interrupts ???? 4-23 4.6.2 RTC Alarm ???? 4-23 4.6.3 System Timer???? 4-23 4.7 External Power Control ???? 4-24 4.7.1 USB PHY (OTG and HOST)???? 4-25 4.7.2 HDMI PHY ???? 4-25 4.7.3 MIPI D-PHY ???? 4-26 4.7.4 PLL ???? 4-26 4.7.5 DAC ???? 4-27 4.7.6 ADC I/O ???? 4-28 4.7.7 POR ???? 4-28 4.8 Internal memory control ???? 4-29 4.8.1 SRAM ???? 4-29 4.8.2 ROM ???? 4-30 4.9 Reset Control ???? 4-31 4.9.1 Reset Types???? 4-31 4.9.2 Hardware Reset???? 4-31 4.10 Register Description???? 4-37 4.10.1 Register Map ???? 4-37 4.10.2 Clock Control Register???? 4-39 4.10.3 Reset Control Register ???? 4-40 4.10.4 Power Management Register ???? 4-41 4.10.5 MISC Register ???? 4-50

     5

     Intelligent Energy Management ????5-1

     5.1 Overview OF Intelligent Energy Management ???? 5-1 5.1.1 Key Features of Intelligent Energy Management ???? 5-2 5.1.2 Block Diagram ???? 5-3 5.2 Functional Description of Intelligent Energy Management ???? 5-4 5.2.1 IEM System Components???? 5-4

     5.2.2 IEM System Operation ???? 5-9 5.3 IEM Implementation and Driver Setting ???? 5-13 5.3.1 Definition of Performance ???? 5-13 5.3.2 HPM Structure and Closed-Loop Behavior ???? 5-14 5.3.3 Initialization Sequence???? 5-17 5.4 I/O Description ???? 5-18 5.5 Register Description???? 5-19 5.5.1 Register Map ???? 5-19 5.5.2 IEC Related Registers ???? 5-22 5.5.3 APC1 Related Registers???? 5-34

     6

     BOOTING SEQUENCE ????6-1

     6.1 Overview of Booting Sequence???? 6-1 6.2 Scenario Description???? 6-3 6.2.1 Reset Status ???? 6-3 6.2.2 Booting Sequence Example ???? 6-4 6.2.3 Fixed PLL and Clock Setting ???? 6-6 6.2.4 OM Pin Configuration ???? 6-7 6.2.5 Secure Booting ???? 6-9

     List of Figures

     Figure Number Figure 2-1 Figure 3-1 Figure 3-2 Figure 3-3 Figure 3-4 Figure 4-1 Figure 4-2 Figure 4-3 Figure 5-1 Figure 5-2 Figure 5-3 Figure 5-4 Figure 5-5 Figure 5-6 Figure 6-1 Figure 6-2 Figure 6-3 Title Page Number

     GPIO Block Diagram ???? 2-7 S5PV210 Clock Domains ???? 3-1 S5PV210 Top-Level Clocks???? 3-2 S5PV210 Clock Generation Circuit 1 ???? 3-10 CLKOUT Waveform with DCLK Divider ???? 3-53 State Transition Diagram of Power Mode???? 4-16 Cortex-A8 Power Mode Transition Diagram???? 4-20 Power ON/OFF & Sleep mode Enter/Exit Sequence ???? 4-33 Intelligent Energy Manager Solution???? 5-1 IEM Block Diagram ???? 5-3 PowerWise Performance Tracking and Voltage Adjustment???? 5-6 IEM Closed-Loop Voltage Generation Flow in HPM and APC1???? 5-14 IEM Closed-Loop Control Flow in APC1 HPM Delay ???? 5-15 HPM Delay Tap structure in S5PV210 ???? 5-16 Block Diagram of Booting Time Operation ???? 6-2 Total Booting Code Sequence Flow Chart ???? 6-4 Secure Booting Diagram???? 6-10

     List of Tables

     Table Number Table 3-1 Table 3-2 Table 3-3 Table 3-4 Table 3-5 Table 3-6 Table 3-7 Table 4-1 Table 4-2 Table 4-3 Table 4-4 Table 4-5 Table 4-6 Table 4-7 Table 4-8 Table 4-9 Table 4-10 Table 5-1 Table 5-2 Table 6-1 Table 6-2 Table 6-3 Title Page Number

     APLL PMS Value ???? 3-5 MPLL PMS Value???? 3-6 EPLL PMS Value ???? 3-6 VPLL PMS Value ???? 3-7 Maximum Operating Frequency for Each Sub-block ???? 3-11 Special Clocks in S5PV210 ???? 3-13 I/O Clocks in S5PV210 ???? 3-14 Comparison of Power Saving Techniques???? 4-2 S5PV210 Power Domains of Internal Logic???? 4-3 Power Mode Summary ???? 4-5 Power Saving Mode Entering/Exiting Condition ???? 4-17 Cortex-A8 Power Control ???? 4-21 Relationship Among Power Mode Wakeup Sources ???? 4-23 S5PV210 External Power Control???? 4-24 The Status of MPLL and SYSCLK After Wake-Up ???? 4-27 S5PV210 Internal Memory Control ???? 4-29 Register Initialization Due to Various Resets???? 4-36 Example Divider Values for 1600MHz PLL Output???? 5-13 Example Divider Values for 833MHz PLL Output???? 5-13 Functions Needed for Various Reset Status???? 6-3 First Boot Loader's Clock Speed at 24 MHz External Crystal ???? 6-6 OM Pin Setting for Various Booting Option ???? 6-7

     S5PV210_UM

     1 CHIP ID

     1

     CHIP ID

     1.1 OVERVIEW OF CHIP ID

     The S5PV210 includes a Chip ID block for the software (SW) that sends and receives APB interface signals to the bus system. Chip ID is placed on the first address of the SFR region (0xE000_0000). The product ID register supplies product ID, revision number and device ID.

     1-1

     S5PV210_UM

     1 CHIP ID

     1.2 REGISTER DESCRIPTION

     1.2.1 REGISTER MAP Register PRO_ID Address 0xE000_0000 R/W R Description Product information Reset Value 0x43110020

     1.2.1.1 Product ID Register (PRO_ID, R, Address = 0xE000_0000) PRO_ID Product ID Reserved Rev. Number Device ID Bit [31:12] [11:8] [7:4] [3:0] Description Product ID The product ID allocated to S5PV210 is ??0x43110?? Reserved bits Revision Number Device ID 000 = V210 001 = C110 010 = C111 Others = reserved Initial State 0x43110 0x2 0x0

     1-2

     S5PV210_UM

     2 GENERAL PURPOSE INPUT/OUTPUT

     2

     x x x x x x x x x x x x x x x x x x

     GENERAL PURPOSE INPUT/ OUTPUT

     This chapter describes the General Purpose Input/ Output (GPIO).

     2.1 OVERVIEW

     S5PV210 includes 237 multi-functional input/ output port pins and 142 memory port pins. There are 34 general port groups and 2 memory port groups as listed below: GPA0: 8 in/out port - 2xUART with flow control GPA1: 4 in/out port - 2xUART without flow control or 1xUART with flow control GPB: 8 in/out port - 2x SPI GPC0: 5 in/out port - I2S, PCM, AC97 GPC1: 5 in/out port - I2S, SPDIF, LCD_FRM GPD0: 4 in/out port - PWM GPD1: 6 in/out port - 3xI2C, PWM, IEM GPE0,1: 13 in/out port - Camera I/F GPF0,1,2,3: 30 in/out port - LCD I/F GPG0,1,2,3: 28 in/out port - 4xMMC channel (Channel 0 and 2 support 4-bit and 8-bit mode, but channel 1, and channel 3 support only 4-bit mode) GPH0,1,2,3: 32 in/out port - Key pad, External Wake-up (up-to 32-bit). (GPH* groups are in Alive region) GPI: Low Power I2S, PCM (in/out port is not used), PDN configuration for power down is controlled by AUDIO_SS PDN Register. GPJ0,1,2,3,4: 35 in/out port - Modem IF, CAMIF, CFCON, KEYPAD, SROM ADDR[22:16] MP0_1,2,3: 20 in/out port - Control signals of EBI (SROM, NF, OneNAND) MP0_4,5,6,7: 32 in/out memory port - EBI (For more information about EBI configuration, refer to Chapter 5, and 6) MP1_0~8: 71 DRAM1 ports (in/out port is not used) MP2_0~8: 71 DRAM2 ports (in/out port is not used) ETC0, ETC1, ETC2, ETC4: 28 in/out ETC ports - JTAG, Operating Mode, RESET, CLOCK (ETC3 is reserved)

     2-1

     S5PV210_UM

     2 GENERAL PURPOSE INPUT/OUTPUT

     2.1.1 FEATURES The key features of GPIO include: x x x x Controls 146 GPIO Interrupts Controls 32 External Interrupts 237

    multi-functional input / output ports Controls pin states in Sleep Mode except GPH0, GPH1, GPH2, and GPH3 ( GPH* pins are alive-pads)

     2.1.2 INPUT/ OUTPUT CONFIGURATION Configurable Input/ Output (I/O) is subdivided into Type A and Type B.

     2.1.3 S5PV210 INPUT/ OUTPUT TYPES I/O Types A I/O Group GPA0, GPA1, GPC0, GPC1, GPD0, GPD1, GPE0, GPE1, GPF0, GPF1, GPF2, GPF3, GPH0, GPH1, GPH2, GPH3, GPI, GPJ0, GPJ1, GPJ2, GPJ3, GPJ4 GPB, GPG0, GPG1, GPG2, GPG3, MP0 Description Normal I/O (3.3V I/O) Fast I/O (3.3V I/O) DRAM I/O (1.8V IO)

     B

     C

     MP1, MP2

     2-2

     S5PV210_UM

     2 GENERAL PURPOSE INPUT/OUTPUT

     2.1.4 IO DRIVER STRENGTH 2.1.4.1 Type A IO Driver Strength ( VDD=3.3V

    0.3V) Currents Parameter Worst Typical Best VDD=3.00V VDD=3.30V VDD=3.60V T=125 T=25 T=-40 Process=Slow Process=Nominal Process=Fast Isink at VDD*0.2V Isink at VDD*0.2V Isink at VDD*0.2V Isource at VDD*0.8V Isource at VDD*0.8V Isource at VDD*0.8V Isink Isource Isink Isource Isink Isource Isink Isource 7.005 mA -7.103 mA 11.69 mA -11.37 mA 16.35 mA -17.06 mA 30.38 mA -28.44 mA 11.19 mA -10.88 mA 18.67 mA -17.42 mA 26.12 mA -26.14 mA 48.52 mA -43.56 mA 15.92 mA -15.63 mA 26.54 mA -25.02 mA 37.15 mA -37.53 mA 69.01 mA -62.55 mA

     Driver Type

     DS0=0,DS1=0 DS0=0,DS1=1 3.3V IO DS0=1,DS1=0 DS0=1,DS1=1

     ( VDD=2.5V 0.2V) Currents Parameter Worst Typical Best VDD=2.30V VDD=2.50V VDD=2.70V T=125 T=25 T=-40 Process=Slow Process=Nominal Process=Fast Isink at VDD*0.2V Isink at VDD*0.2V Isink at VDD*0.2V Isource at VDD*0.8V Isource at VDD*0.8V Isource at VDD*0.8V Isink Isource Isink Isource Isink Isource Isink Isource 4.497 mA -4.405 mA 7.501 mA -7.053 mA 10.50 mA -10.58 mA 19.50 mA -17.63 mA 7.461 mA -6.993 mA 12.44 mA -11.19 mA 17.41 mA -16.79 mA 32.35 mA -27.98 mA 11.12 mA -10.42 mA 18.55 mA -16.67 mA 25.96 mA -24.75 mA 48.22 mA -41.68 mA

     Driver Type

     DS0=0,DS1=0 DS0=0,DS1=1 3.3V IO DS0=1,DS1=0 DS0=1,DS1=1

     2-3

     S5PV210_UM

     2 GENERAL PURPOSE INPUT/OUTPUT

     ( VDD=1.8V 0.15V) Currents Parameter Worst Typical Best VDD=1.65V VDD=1.80V VDD=1.95V T=12 T=25 T=-40 Process=Slow Process=Nominal Process=Fast Isink at VDD*0.2V Isink at VDD*0.2V Isink at VDD*0.2V Isource at VDD*0.8V Isource at VDD*0.8V Isource at VDD*0.8V Isink Isource Isink Isource Isink Isource Isink Isource 2.263 mA -2.272 mA 3.775 mA -3.636 mA 5.282 mA -5.454 mA 9.813 mA -9.091 mA 4.057 mA -3.835 mA 6.767 mA -6.136 mA 9.469 mA -9.204 mA 17.59 mA -15.34 mA 6.568 mA -6.081 mA 10.95 mA -9.729 mA 15.33 mA -14.59 mA 28.48 mA -24.32 mA

     Driver Type

     DS0=0,DS1=0 DS0=0,DS1=1 3.3V IO DS0=1,DS1=0 DS0=1,DS1=1

     NOTE: 1. Isink is measured at 0.2 x VDD NOTE: 2. Isource is measured at 0.8 X VDD

     - Mesured point is different from measurement spec of 65nm IO Driver

     2.1.4.2 Type B IO Driver Strength ( VDD=3.3V 0.3V ) Currents Parameter Worst Typical Best VDD=3.00V VDD=3.30V VDD=3.60V T=125 T=25 T=-40 Process=Slow Process=Nominal Process=Fast Isink at VDD*0.2V Isink at VDD*0.2V Isink at VDD*0.2V Isource at Isource at VDD*0.8V Isource at VDD*0.8V VDD*0.8V Isink Isource Isink Isource Isink Isource Isink Isource 2.79mA -2.78mA 11.18mA -11.11mA 19.56mA -19.44mA 27.95mA -27.77mA 4.49mA -4.26mA 17.98mA -17.04mA 31.46mA -29.81mA 44.94mA -42.59mA 6.47mA -6.12mA 25.88mA -24.49mA 45.29mA -42.86mA 64.7mA

-61.24mA

     Driver Type

     DS0=0,DS1=0 DS0=0,DS1=1 3.3V IO DS0=1,DS1=0 DS0=1,DS1=1

     2-4

     S5PV210_UM

     2 GENERAL PURPOSE INPUT/OUTPUT

     ( VDD=2.5V 0.2V ) Currents Parameter Worst Typical Best VDD=2.30V VDD=2.50V VDD=2.70V T=125 T=25 T=-40 Process=Slow Process=Nominal Process=Fast Isink at VDD*0.2V Isink at VDD*0.2V Isink at VDD*0.2V Isource at Isource at VDD*0.8V Isource at VDD*0.8V VDD*0.8V Isink Isource Isink Isource Isink Isource Isink Isource 1.85mA -1.72mA 7.41mA -6.88mA 12.97mA -12.04mA 18.53mA -17.19mA 3.05mA -2.73mA 12.22mA -10.93mA 21.38mA -19.12mA 30.54mA -27.32mA 4.53mA -4.08mA 18.11mA -16.3mA 31.69mA -28.52mA 45.27mA -40.75mA

     Driver Type

     DS0=0,DS1=0 DS0=0,DS1=1 3.3V IO DS0=1,DS1=0 DS0=1,DS1=1

     ( VDD=1.8V 0.15V ) Currents Parameter Worst Typical Best VDD=1.65V VDD=1.80V VDD=1.95V T=12 T=25 T=-40 Process=Slow Process=Nominal Process=Fast Isink at VDD*0.2V Isink at VDD*0.2V Isink at VDD*0.2V Isource at Isource at VDD*0.8V Isource at VDD*0.8V VDD*0.8V Isink Isource Isink Isource Isink Isource Isink Isource 0.99mA -0.91mA 3.96mA -3.63mA 6.93mA -6.35mA 9.9mA -9.06mA 1.73mA -1.53mA 6.93mA -6.1mA 12.12mA -10.68mA 17.32mA -15.26mA 2.74mA -2.41mA 10.94mA -9.64mA 19.14mA -16.88mA 27.35mA -24.11mA

     Driver Type

     DS0=0,DS1=0 DS0=0,DS1=1 3.3V IO DS0=1,DS1=0 DS0=1,DS1=1

     NOTE: 1. Isink is measured at 0.2 x VDD NOTE: 2. Isource is measured at 0.8 X VDD

     - Mesured point is different from measurement spec of 65nm IO Driver

     2-5

     S5PV210_UM

     2 GENERAL PURPOSE INPUT/OUTPUT

     2.1.4.3 Type C IO Driver Strength ( VDD=1.8V VDDx10% ) Currents Parameter Worst Typical Best VDD=1.65V VDD=1.80V VDD=1.95V T=125 T=25 T=-25 Process=Slow Process=Nominal Process=Fast Isink at VDD*0.2V Isink at VDD*0.2V Isink at VDD*0.2V Isource at VDD*0.8V Isource at VDD*0.8V Isource at VDD*0.8V Isink Isource Isink Isource Isink Isource Isink Isource 3.37mA -2.62mA 6.74mA -6.10mA 10.10mA -6.97mA 11.77mA -11.32mA 5.60mA -4.32mA 11.21mA -10.08mA 16.80mA -11.51mA 19.59mA -18.70mA 8.36mA -6.67mA 16.73mA -15.58mA 25.07mA -17.80mA 29.24mA -28.90mA

     Driver Type

     DS0=0,DS1=0 DS0=0,DS1=1 1.8V MDDR IO DS0=1,DS1=0 DS0=1,DS1=1

     ( VDD=1.2V VDDx10% ) Currents Parameter Worst Typical Best

    VDD=1.045V VDD=1.1V VDD=1.155V T=125 T=25 T=-25 Process=Slow Process=Nominal Process=Fast Isink at VDD*0.2V Isink at VDD*0.2V Isink at VDD*0.2V Isource at VDD*0.8V Isource at VDD*0.8V Isource at VDD*0.8V Isink Isource Isink Isource Isink Isource Isink Isource 1.10mA -1.05mA 2.20mA -2.45mA 3.30mA -2.80mA 3.85mA -4.55mA 2.22mA -1.92mA 4.45mA -4.49mA 6.67mA -5.12mA 7.78mA -8.32mA 3.95mA -3.30mA 7.91mA -7.70mA 11.86mA -8.79mA 13.82mA -14.29mA

     Driver Type

     DS0=0,DS1=0 DS0=0,DS1=1 1.8V MDDR IO DS0=1,DS1=0 DS0=1,DS1=1

     NOTE: 1. Isink is measured at 0.2 x VDD NOTE: 2. Isource is measured at 0.8 X VDD

     - Mesured point is different from measurement spec of 65nm IO Driver

     2-6

     S5PV210_UM

     2 GENERAL PURPOSE INPUT/OUTPUT

     2.1.5 INPUT/ OUTPUT DESCRIPTION 2.1.5.1 General Purpose Input/Output Block Diagram GPIO consists of two parts, namely, alive-part and off-part. In Alive-part power is supplied on sleep mode, but in off-part it is not the same. Therefore, the registers in alive-part keep their values during sleep mode.

     Register File

     Mux control

     Pad control

     APB Bus

     APB Interface

     External Interrupt Control

     Interrupt Controller

     Off Part

     Async Interface

     Mux control

     Pad control

     Register File

     External Interrupt Control

     Interrupt Controller & Wake -up controller

     Alive Part

     Figure 2-1

     GPIO Block Diagram

     2-7

     S5PV210_UM

     2 GENERAL PURPOSE INPUT/OUTPUT

     2.1.5.2 Pin Summary I/O Control Type A1 A2 A3 A4 A5 B1 B2 Function Description Control at power down mode is possible, power down mode is released by S/W (ENABLE_GPIO bit of OTHERS register at PMU) Control at power down mode is possible, power down mode is released by S/W

    (ENABLE_UART_IO bit of OTHERS register at PMU) Control at power down mode is possible, power down mode is released by S/W (ENABLE_MMC_IO bit of OTHERS register at PMU) Control at power down mode is possible, power down mode is released by H/W automatically Control at power down mode is possible, power down mode is released by H/W (ENABLE_CF_IO bit of OTHERS register at PMU) No Retention (Alive IO) No Retention (Analog IO)

     2-8

     S5PV210_UM

     2 GENERAL PURPOSE INPUT/OUTPUT

     2.1.5.3 Pin Mux Description

     @Reset Pin Name GPIO Func0 Func1 Func2 Func3 Default PUD XuRXD[0] XuTXD[0] XuCTSn[0] XuRTSn[0] XuRXD[1] XuTXD[1] XuCTSn[1] XuRTSn[1] XuRXD[2] GPA0[0] GPA0[1] GPA0[2] GPA0[3] GPA0[4] GPA0[5] GPA0[6] GPA0[7] GPA1[0] UART_0_RXD UART_0_TXD UART_0_CTSn UART_0_RTSn UART_1_RXD UART_1_TXD UART_1_CTSn UART_1_RTSn UART_2_RXD UART_AUDIO_ RXD UART_AUDIO_ TXD UART_2_CTSn UART_2_RTSn GPI GPI GPI GPI GPI GPI GPI GPI GPI PD PD PD PD PD PD PD PD PD I/O I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) State A1 A1 A1 A1 A1 A1 A1 A1 A2 PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G Sleep Pad Type

     XuTXD[2] XuRXD[3] XuTXD[3] XspiCLK[0] XspiCSn[0] XspiMISO[0] XspiMOSI[0] XspiCLK[1] XspiCSn[1] XspiMISO[1] XspiMOSI[1] Xi2s1SCLK Xi2s1CDCLK Xi2s1LRCK Xi2s1SDI Xi2s1SDO Xpcm2SCLK Xpcm2EXTCLK Xpcm2FSYNC Xpcm2SIN Xpcm2SOUT XpwmTOUT[0] XpwmTOUT[1] XpwmTOUT[2] XpwmTOUT[3]

     GPA1[1] GPA1[2] GPA1[3] GPB[0] GPB[1] GPB[2] GPB[3] GPB[4] GPB[5] GPB[6] GPB[7] GPC0[0] GPC0[1] GPC0[2] GPC0[3] GPC0[4] GPC1[0] GPC1[1] GPC1[2] GPC1[3] GPC1[4] GPD0[0] GPD0[1] GPD0[2] GPD0[3]

     UART_2_TXD UART_3_RXD UART_3_TXD SPI_0_CLK SPI_0_nSS SPI_0_MISO SPI_0_MOSI SPI_1_CLK SPI_1_nSS SPI_1_MISO SPI_1_MOSI I2S_1_SCLK I2S_1_CDCLK I2S_1_LRCK I2S_1_SDI I2S_1_SDO PCM_2_SCLK PCM_2_EXTCLK PCM_2_FSYNC PCM_2_SIN PCM_2_SOUT TOUT_0 TOUT_1 TOUT_2 TOUT_3 PCM_1_SCLK PCM_1_EXTCLK PCM_1_FSYNC PCM_1_SIN PCM_1_SOUT SPDIF_0_OUT SPDIF_EXTCLK LCD_FRM

     GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI

     PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD

     I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L)

     A2 A2 A2 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1

     PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRF_G PBIDIRF_G PBIDIRF_G PBIDIRF_G PBIDIRF_G PBIDIRF_G PBIDIRF_G PBIDIRF_G PBIDIRSE_G

    PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G

     AC97BITCLK AC97RESETn AC97SYNC AC97SDI AC97SDO I2S_2_SCLK I2S_2_CDCLK I2S_2_LRCK I2S_2_SDI I2S_2_SDO

     GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI

     2-9

     S5PV210_UM

     2 GENERAL PURPOSE INPUT/OUTPUT

     @Reset Pin Name GPIO Func0 Func1 Func2 Func3 Default PUD Xi2c0SDA Xi2c0SCL Xi2c1SDA Xi2c1SCL Xi2c2SDA Xi2c2SCL XciPCLK XciVSYNC XciHREF XciDATA[0] XciDATA[1] XciDATA[2] XciDATA[3] XciDATA[4] XciDATA[5] XciDATA[6] XciDATA[7] XciCLKenb XciFIELD XvHSYNC XvVSYNC XvVDEN XvVCLK XvVD[0] XvVD[1] XvVD[2] XvVD[3] XvVD[4] XvVD[5] XvVD[6] XvVD[7] XvVD[8] XvVD[9] XvVD[10] XvVD[11] XvVD[12] GPD1[0] GPD1[1] GPD1[2] GPD1[3] GPD1[4] GPD1[5] GPE0[0] GPE0[1] GPE0[2] GPE0[3] GPE0[4] GPE0[5] GPE0[6] GPE0[7] GPE1[0] GPE1[1] GPE1[2] GPE1[3] GPE1[4] GPF0[0] GPF0[1] GPF0[2] GPF0[3] GPF0[4] GPF0[5] GPF0[6] GPF0[7] GPF1[0] GPF1[1] GPF1[2] GPF1[3] GPF1[4] GPF1[5] GPF1[6] GPF1[7] GPF2[0] I2C0_SDA I2C0_SCL I2C1_SDA I2C1_SCL I2C2_SDA I2C2_SCL CAM_A_PCLK CAM_A_VSYNC CAM_A_HREF CAM_A_DATA[0] CAM_A_DATA[1] CAM_A_DATA[2] CAM_A_DATA[3] CAM_A_DATA[4] CAM_A_DATA[5] CAM_A_DATA[6] CAM_A_DATA[7] CAM_A_CLKOUT CAM_A_FIELD LCD_HSYNC LCD_VSYNC LCD_VDEN LCD_VCLK LCD_VD[0] LCD_VD[1] LCD_VD[2] LCD_VD[3] LCD_VD[4] LCD_VD[5] LCD_VD[6] LCD_VD[7] LCD_VD[8] LCD_VD[9] LCD_VD[10] LCD_VD[11] LCD_VD[12] SYS_CS0 SYS_CS1 SYS_RS SYS_WE SYS_VD[0] SYS_VD[1] SYS_VD[2] SYS_VD[3] SYS_VD[4] SYS_VD[5] SYS_VD[6] SYS_VD[7] SYS_VD[8] SYS_VD[9] SYS_VD[10] SYS_VD[11] SYS_VD[12] VEN_HSYNC VEN_VSYNC VEN_HREF V601_CLK VEN_DATA[0] VEN_DATA[1] VEN_DATA[2] VEN_DATA[3] VEN_DATA[4] VEN_DATA[5] VEN_DATA[6] VEN_DATA[7] V656_DATA[0] V656_DATA[1] V656_DATA[2] V656_DATA[3] V656_DATA[4] IEM_SCLK IEM_SPWI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD I/O I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L) I(L)

     Sleep Pad Type State A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G PBIDIRSE_G

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