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ug333_S3AN_In_System_Flash_User_Guide_v2_1

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ug333_S3AN_In_System_Flash_User_Guide_v2_1

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     Spartan-3AN FPGA In-System Flash User Guide

     For Spartan?-3AN FPGA applications that read or write data to or from the In-System Flash memory after configuration

     UG333 (v2.1) January 15, 2009

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     Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information. THE DOCUMENTATION IS DISCLOSED TO YOU ??AS-IS?? WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION. ? 2007?C2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

     Revision History

     The following table shows the revision history for this document.

     Date 02/26/07 08/29/07 Version 1.0 1.1 Initial release. Updated throughout. Removed legacy commands not recommended for designs. Added ??MultiBoot Configuration Bitstream Guidelines??. Simplified discussion in Chapter 7, ??Power Management??. Added Caution to Chapter 1, ??Overview and SPI_ACCESS Interface,??, that SPI_ACCESS is not currently supported in simulation. Updated to reflect current simulation model and timing characteristics. Added ??Related Materials

    and References,?? page 14 to Chapter 1, ??Overview and SPI_ACCESS Interface??. Updated and clarified default SIM_FACTORY_ID in Table 1-3. Corrected highest byte number in Figure 2-5. Revision

     09/24/07 04/22/08 01/15/09

     1.1.1 2.0 2.1

     Spartan-3AN FPGA In-System Flash User Guide

     www.xilinx.com

     UG333 (v2.1) January 15, 2009

     Table of Contents

     Chapter 1: Overview and SPI_ACCESS Interface

     In-System Flash

    Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Accessing In-System Flash Memory After Configuration . . . . . . . . . . . . . . . . . . . . . . 9

     SPI_ACCESS Design

    Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 HDL Instantiation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . . 10

    VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SPI

    Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Example Detailed Command

    Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    12 Simulation

    Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

     Related Materials and

    References . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . 14

     Chapter 2: In-System Flash Memory Architecture

     Block

    Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Flash Memory

    Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Addressing Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . . . . . . . . . . 17

     Addressing

    Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Default Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . . 19

     Delivered

    State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Memory Allocation

    Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . . . . 20 MultiBoot Configuration Bitstream Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

     Align to Flash Sector

    Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . 26 Additional Memory Space Required for DCM_WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . 26

     User Data Storage

    Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . . . 27

     Chapter 3: Read Commands

     Fast

    Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Random

    Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page to Buffer

    Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . . . . . . . . . Buffer Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     30 31 33 35

     Chapter 4: Write and Program Commands

     Buffer

    Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Buffer to Page Program with Built-in

    Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Buffer to Page Program without Built-in

    Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page Program Through

    Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . Page to Buffer Compare (Program

    Verify) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pre-initializing SRAM Page Buffer

    Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM-Like, Byte-Level Write

    Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sequential vs. Random Page Programming, Cumulative

    Operations . . . . . . . . .

     40 41 41 44 46 47 48 48

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     Auto Page

    Rewrite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

     Chapter 5: Erase Commands

     Sector Protect and Sector Lockdown Prevent Erase

    Operations . . . . . . . . . . . . . . . Erased

    State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page

    Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block

    Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sector

    Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     51 51 52 54

     57 Sector

    Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Default Addressing

    Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Operation

    Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

     Chapter 6: Status and Information Commands

     Status

    Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

    READY/BUSY . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISF Memory

    Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . . . . . . . . . . Sector Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 65 65 65 66

     Status Register

    Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . . . . . . . . . 66 Information Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

     Manufacturer

    Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . . . . . . . . Family Code/Memory Density

    Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Memory Type/Product Version

    Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extended Device Information

    Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    68 69 69 69

     Chapter 7: Power Management

     Active

    Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Standby

    Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

     Chapter 8: Sector-Based Program/Erase Protection

     Sector

    Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

     Sector Protection Status at

    Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Sector Protection

    Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . . . . . Sector Protection Register

Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Sector Protection Register

    Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Unprotecting Sectors While Sector Protection

    Enabled . . . . . . . . . . . . . . . . . . . . . . . . . Sector Protection Register Limited to 10,000 Program/Erase Cycles . . . . . . . . . . . . . . . Sector Protection Register

    Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . Sector Protection

    Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . . . . . Sector Protection Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 74 75 76 77 78 78 79 79

     Sector

    Lockdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

     Sector Lockdown

    Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Sector Lockdown

    Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . . . . 81 Sector Lockdown Register Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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     Chapter 9: Security Register

     Security

    Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Security Register

    Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Security Register Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . . . . . . . 85

     Appendix A: Optional Power-of-2 Addressing Mode

     How to Determine the Current Addressing

    Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Permanently Changing to the Power-of-2 Addressing Mode . . . . . . . . . . . . . . . . . 88 Power-of-2 Addressing

    Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

     Power-of-2

    Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . . . . . . . . Power-of-2 Page Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . . . Power-of-2 Block Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . Power-of-2 Sector

    Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . .

     . . . . . . . . . . . . . . . . . . 89 89 90 90

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     Chapter 1

     Overview and SPI_ACCESS Interface

     Note: This user guide only applies to Spartan?-3AN FPGA designs that access or modify the insystem Flash after configuration. This user guide is not required for applications that only use the insystem Flash to configure the FPGA. For Spartan-3AN FPGA configuration information, see UG332: Spartan-3 Generation Configuration User Guide.

     Spartan-3AN FPGAs include abundant In-System Flash (ISF) memory. The ISF memory array appears to a Spartan-3AN FPGA application as SPI-based serial Flash memory. The ISF memory is primarily designed to automatically configure the FPGA when power is applied or whenever the PROG_B pin is pulsed Low. However, the ISF memory array is large enough to store?? ? two complete, uncompressed FPGA configuration bitstreams. Using the MultiBoot feature, the FPGA application can selectively choose between the two designs or reserve one image as a fail-safe image for live in-system Flash updates. additional nonvolatile data for the FPGA application, such as MicroBlaze? processor code, serial numbers, Ethernet MAC IDs, graphic images, message templates, and so on.

     In-System Flash Summary

     Table 1-1, page 8 summarizes the key attributes and capabilities of the ISF memory. The remainder of this user guide describes these features and capabilities in greater detail. The table also summarizes the amount of Flash memory available to the FPGA application, depending on the number of design options. ? How many FPGA configuration bitstreams are stored in the ISF array?

     ?

     Most applications store a single FPGA configuration bitstream,

    leaving the remaining space for nonvolatile user data. Optionally, each Spartan-3AN FPGA can store two uncompressed MultiBoot configuration images, which reduces the amount of Flash memory available to the application.

     Does the FPGA application use the ISF memory??s Sector Protect or Sector Lockdown features to protect ISF memory contents?

     Without using the sector-based data protection features, user application data can be stored in the next available page location following the FPGA bitstream (page aligned). If the application uses the sector-based data protection features, then user application data is typically aligned to the next sector boundary (sector aligned).

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     Chapter 1: Overview and SPI_ACCESS Interface

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     Table 1-1:

     In-System Flash Memory Summary

     Spartan-3AN FPGA Description 3S50AN 1,081,344 (1M+) 1 264 256 512 64 4 8 128 2,112 33,792 437,312 208 214 Default Power-of-2 3S200AN 4,325,376 (4M+) 2 264 256 2,048 256 8 8 256 2,112 67,584 1,196,128 567 585 3S400AN 4,325,376 (4M+) 2 264 256 2,048 256 8 8 256 2,112 67,584 1,886,560 894 922 3S700AN 8,650,752 (8M+) 2 264 256 4,096 512 16 8 256 2,112 67,584 2,732,640 1,294 1,335 3S1400AN 17,301,504 (16M+) 2 528 512 4,096 512 16 8 256 4,224 135,168 4,755,296 1,126 1,161

     In-System Flash (ISF) memory bits SRAM page buffers Default Addressing Mode page size (bytes) Optional Power-of-2 Addressing Mode page size (bytes) Pages Blocks Sectors Pages per Block Pages per Sector Bytes per Block Bytes per Sector FPGA configuration bitstream size (uncompressed) Pages required for FPGA bitstream, always starting at page 0

     Page Aligned User Data (maximizes available data space but limits Sector Protect, Sector Lockdown features) Pages available for user application beyond FPGA configuration bitstream, data aligned to next page boundary, Default Addressing Mode Total Flash memory bits available for user application, Default Addressing Mode 304 642,048 (627K) (0.61M) 2 2 540,672 (528K) (0.51M) 1,481 3,127,872 (3,054K) (2.98M) 3 5 2,703,360 (2,640K) (2.57M) 1,154 2,437,248 (2,380K) (2.32M) 4 4 2,162,688 (2,112K) (2.06M) 2,802 5,917,824 (5,779K) (5.64M) 6 10 5,406,720 (5,280K) (5.15M) 2,970 12,545,280 (12,251K) (11.96M) 5 11 11,894,784 (11,616K) (11.34M)

     Sector Aligned User Data (user data aligned to sectors for Sector Protect, Sector Lockdown features) Sectors required per uncompressed

    FPGA bitstream Sectors available for user application beyond FPGA configuration bitstream, aligned to next sector boundary Total bits available for user application in remaining sectors, Default Addressing Mode MultiBoot FPGA Configuration Maximum number of uncompressed MultiBoot FPGA configuration images Total sectors available for user application, beyond MultiBoot FPGA configuration bitstreams Total Flash memory bits available for user application, beyond MultiBoot FPGA configuration bitstreams, sector aligned, Default Addressing Mode 2 0 2 2 1,081,344 (1,056K) (1.03M) 2 0 2 4 2,162,688 (2,112K) (2.06M) 2 6 6,488,064 (6,336K) (6.18M)

     0

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     Accessing In-System Flash Memory After Configuration

     Accessing In-System Flash Memory After Configuration

     SPI_ACCESS Design Primitive

     After the FPGA configures, the application loaded into the FPGA can access the ISF memory using a special design primitive called SPI_ACCESS, shown in Figure 1-1. All data accesses to and from the ISF memory are performed using an SPI serial protocol. Neither the Spartan-3AN FPGA itself nor the SPI_ACCESS primitive includes a dedicated SPI master controller. Instead, the control logic is implemented using the FPGA??s programmable logic resources. The SPI_ACCESS primitive essentially connects the FPGA application to the In-System Flash memory array.

     SPI_ACCESS

     MOSI CSB CLK

     UG332_C13_06_081506

     MISO

     Figure 1-1:

     SPI_ACCESS Primitive (only available on Spartan-3AN FPGAs)

     Table 1-2 describes the connections to the SPI_ACCESS primitive. The serial data lines are names relating to the logic that drives the data. The FPGA application is always the Master of each SPI transaction; the ISF memory is always the Slave. Table 1-2: SPI_ACCESS Primitive Connections

     Direction Output Input Input Input Function Master Input, Slave Output. Serial data output from the ISF memory array back to the FPGA logic. Master Output, Slave Input. Serial data input to the ISF memory array from the FPGA logic. Active-Low chip-enable to ISF memory array, driven by FPGA logic. Clock input to ISF memory array, driven by FPGA

logic.

     Port Name MISO MOSI CSB CLK

     Table 1-3 describes the available attributes for the SPI_ACCESS primitive. Table 1-3:

     Attribute SIM_DEVICE

     SPI_ACCESS Primitive Attributes

     Type String Allowed Values ??3S50AN??, ??3S200AN??, ??3S400AN??, ??3S700AN?? or ??3S1400AN?? Any 64-byte hex value Default Description

     ??UNSPECIFIED?? Specifies the target device so that the proper size SPI Memory is used. This attributes required to be set.

     SIM_USER_ID

     64-byte Hex Value

     All locations default to 0xFF

     Specifies the programmed USER ID in the Security Register for the SPI Memory

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     Table 1-3:

     Attribute

     SPI_ACCESS Primitive Attributes (Continued)

     Type String Allowed Values Specified file and directory name Any 64-byte Hex Value Default ??NONE?? Description Optionally specifies a hex file containing the initialization memory content for the SPI Memory. Specifies the unique identifier value in the Security Register for simulation purposes (the actual hardware value will be specific to the particular device used). See ??Security Register?? in Chapter 9. Scales down some timing delays for faster simulation run. ??ACCURATE?? = timing and delays consistent with datasheet specs. ??SCALED?? = timing numbers scaled back to run faster simulation, behavior not affected.

     SIM_MEM_FILE

     SIM_FACTORY_ID

     64-byte Hex Value

     All locations default to 0x00

     SIM_DELAY_TYPE

     String

     ??ACCURATE??, ??SCALED??

     ??SCALED??

     HDL Instantiation Examples

     The SPI_ACCESS design primitive must be instantiated in an HDL design;

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