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Measurements and Modelling of Delay Lines on Printed Circuit Boards

Scott D. Powers and Jose M. Cruz

2000 Sun Microsystems, Inc. All rights reserved. The SML Technical Report Series is published by Sun Microsystems Laboratories, of Sun Microsystems, Inc. Printed in U.S.A. Unlimited copying without fee is permitted provided that the copies are not made nor distributed for direct commercial advantage, and credit to the source is given. Otherwise, no part of this work covered by copyright hereon may be reproduced in any form or by any means graphic, electronic, or mechanical, including photocopying, recording, taping, or storage in an information retrieval system, without the prior written permission of the copyright owner. TRADEMARKS Sun, Sun Microsystems, the Sun logo, Java, and Solarisare trademarks or registered trademarks of Sun Microsystems, Inc. in the U.S. and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the U.S. and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc. For information regarding the SML Technical Report Series, contact Jeanie Treichel, Editor-in-Chief

Measurements and Modelling of Delay Lines on Printed Circuit Boards

Scott D. Powers and Jose M. Cruz

SMLI TR-2000-92

September 2000

Abstract: Traces on printed circuit boards (PCBs) are often turned into meandering lines to introduce an additional delay. This technical report explores the electrical parasitics involved in that practice by reporting measurements of traces fabricated on a test board. Traces that meander have shorter propagation delays than expected due to coupling between segments. Calculations of the time delay reduction are presented and a model is proposed.

M/S MTV29-01 901 San Antonio Road Palo Alto, CA 94303-4900

email address: sdpowers@ieee.org jose.cruz@eng.sun.com

Measurements and Modelling of Delay Lines on Printed Circuit Boards

Scott D. Powers Jose M. Cruz

1.0 Introduction

Designers of printed circuit boards often face the problem illustrated by the example in Figure 1. It is desired to transmit signals 1, 2 and 3 from one chip to the other with precisely the same transmission

delay. However, with the routing pattern in Figure 1a, signal 3 has a longer path and will arrive later. The conventional solution, shown in Figure 1b, arti?cially extends the paths of signals 1 and 2 to match the lengths of all wires. An example where meander lines might be used is as a bus between a processor and memory. Another example is a clock distribution tree between a clock synthesizer and target clocked circuits. Traces such as those for signals 1 and 2 are called serpentine lines or meander lines. In the past, meander lines have been used with the assumption that the extra wire length is electrically identical to a straight section, and no parasitics were introduced. As trace dimensions become smaller and signal frequencies increase, that assumption may no longer be valid. In this report, we present measurements of the time delay through, and characteristic impedance of meander lines as compared to an equivalent length of straight line.

A

A

2 1 2 3 1 B Figure 1b: Equal Wire Lengths 3

B Figure 1a: Unequal Wire Lengths

1

It is seen that the delay through a meander line is shorter than the delay through an equivalent length of straight trace. This is because coupling between the segments of the meander lines shortens the electrical path. The remainder of this report is organized as follows. Section 2 gives the physical background of transmission lines and meander lines, and de?nes terms used in the rest of the report. Section 3 discusses our measurement methods and reports experimental results. In Section 4, we discuss the results, and Section 5 gives a model for the observed effects. Finally, Section 6 gives conclusions.

2.0 Background

2.1 Meander Line Parameters A meandering section of a PCB trace might look like the wire of Figure 2. The straight path between points A and D is interrupted by several zigzagging segments. We de?ne N as the number of segments in the meander section, l as the length of each section, and d as the pitch (center-tocenter spacing of adjacent traces). In practice, meandering sections are not always rectangular as shown, in order to ?t into the odd shapes found on a PCB. 2.2 Transmission Line Circuit Theory Digital signals are electromagnetic waves that propagate along guiding structures at a ?nite speed. Because their speed is ?nite, the waves have a non-zero physical extent?ªa wavelength. At any given time, the values of the electric and magnetic ?elds for a particular wave vary with respect to position. Therefore, the voltage and current are different at different points along a wavelength. In this report, we are concerned with wavelengths as small as 1.5 cm, while we are trying to describe wires that are several centimeters long. Clearly, we cannot

consider such a wire as a circuit lumped at a single point. One approach is to model the wires as a succession of sections, which are individually small compared to a wavelength, and therefore can be modelled as lumped elements. Using calculus it is possible to extend this method to sections of in?nitesimal length, and describe wires as distributed circuit elements called transmission lines. d

A N=10

B C

l

D

Figure 2: Meander Line Example

2

A transmission line consists of at least two conductors extending parallel to one another for some length, separated by a non-conducting dielectric. Electromagnetic waves propagate in the dielectric along the length of the line. There are many excellent references for transmission lines and distributed circuit elements [1-5]. In the remainder of this section, we will present some equations and concepts useful in dealing with transmission lines. Capacitance Per Unit Length Symbol: C Units: pF/m The capacitance between two conductors of a transmission line, divided by the length of the line. It depends on the geometry of the transmission line cross-section and the permittivity ( ?Å ) of the dielectric. See Figure 3 for a circuit model of an in?nitesimally small section of transmission line. Inductance Per Unit Length Symbol: L Units: nH/m The inductance of the current loop formed by the two conductors of a transmission line, divided by the length of the line. It depends on the geometry of the transmission line crosssection. See Figure 3. Resistance Per Unit Length Symbol: R Units: ? /m The resistance of the transmission line conductors, per unit length of line. It depends on the geometry of the transmission line cross-section, the conductivity of the conductor material, and the frequency of the signal. Because of the skin effect [1], resistance increases with frequency. See Figure 3. Conductance Per Unit Length Symbol: G Units: S/m High-frequency electromagnetic ?elds in a dielectric cause oscillations in the local polarization of the dielectric. These oscillations dissipate power from the transmitted signal. This effect is usually negligible. See Figure 3.

L

R

C

G

Figure 3: RLGC Model of Transmission Line Section Permittivity and Relative Permittivity Symbol: ?Å and ?Å r Units: F/m and dimensionless Permittivity is the ratio between electric ?eld strength and

electric ?ux density. It is a property of a material. The permittivity of free space is a universal constant with the value ?Å 0 = 8.854 pF/m. The total permittivity of a material is found by multiplying ?Å 0 and ?Å r . ?Å = ?År ? ?Å0 (2-1)

3

We will use 4.3 as the relative permittivity of FR-4, a material commonly used as a dielectric in PCBs. Wave Velocity Symbol: v Units: m/s The velocity at which the signal propagates. It depends on the relative permittivity of the dielectric and is given by Equation 2-2: c v = ?År c is the speed of light in a vacuum, which is 3x108 m/s. Characteristic Impedance Symbol: Z0 Units: ? De?ned by Equation 2-3, the characteristic impedance is a property of the line. It is the input impedance of the line, but no power is dissipated by this impedance. L (2-3) Z 0 = --C Re?ection Coef?cient Symbol: ?Ñ or ?? Units: Dimensionless When a wave hits an impedance discontinuity, either at the boundary between two transmission lines of different Z0 or when entering or leaving a transmission line, part of the wave is re?ected and part is transmitted. The re?ection coef?cient, as shown in the ?rst part of Equation 2-4, gives the fraction of the incident wave amplitude that is re?ected. The value of ?Ñ is bounded by -1 and 1. The second part of Equation 2-4 shows how ?Ñ may be calculated; Z1 refers to the input impedance of the network on which the wave is incident. V reflected Z1 ?C Z0 ?Ñ = = V incident Z1 + Z0 (2-4) (2-2)

Scattering Parameters (S-parameters) Symbol: S11, S12, S21, and S22 Units: Dimensionless S-parameters are a generalization of the re?ection coef?cient. They include transmission information and are complex quantities. In the two-port network of Figure 4 for example, S11 gives the fraction of the wave input at port 1 that returns out of port 1, and S21 is the fraction of the wave input at port 1 that transmits to port 2. S-parameters can be displayed in magnitudephase form as a function of frequency, or in a polar plot known as a Smith chart, parameterized by frequency. S11 Port 1 S12 Figure 4: Two-Port Network Port 2 S22 S21

4

Metal (copper) Dielectric (FR-4)

Microstrip

Stripline Figure 5: Common PCB Trace Geometries

Dual Stripline

2.3 Printed Circuit Boards and Traces A quick review of PCB trace terminology is in order. Figure 5 (not to scale) shows cross-sections of typical wire geometries. A microstrip is a trace that runs on the surface of a board and has a nearby reference plane. Striplines are signals enclosed in adjacent reference planes. The ?nal geometry is the most common--a dual stripline where two signal layers are routed

between two reference planes, usually power and ground. Usually the routing directions of the two layers are perpendicular (orthogonal dual striplines), though this is not shown here. The dual stripline geometry is also called asymmetric stripline. 2.4 Characterization Methods 2.4.1 Time-Domain Transmission (TDT) In TDT, a fast step function in voltage is put into the input of a network under test and the output is watched. TDT is useful in measuring delay through a network and looking for distortion. TDT is not very useful for extracting a circuit model since the effects of all the components in the network under test are superimposed at one point in time. 2.4.2 Time-Domain Re?ectometry (TDR) TDR is a measurement method which probes a network by exciting it with a step and watching the re?ections. Background on the principles of TDR can be found in [1]. A TDR graph shows re?ection coef?cient (as observed at the source) as a function of time. A series inductance shows up as a peak, a shunt capacitance shows up as a dip, and a transmission line is a horizontal line where height corresponds to its characteristic impedance. A lossy transmission line has an upward slope. Normalized characteristic impedance at any point can be calculated by Equation 2-5: 1+?Ñ Z 1 = ? Z 0 (2-5) 1?C?Ñ where Z0 is the characteristic impedance of the test equipment (usually 50 ? ).

5

2.4.3 Network Analysis A network analyzer characterizes a two-port system in the frequency domain. At each of several frequencies, the network analyzer injects a sine wave into each port of the network in turn, then measures the transmitted and re?ected waves to compute the S-parameters.

3.0 Measurements of Meander Lines

3.1 Test Setup In this section, we present time-domain and network analyzer measurements for three actual asymmetric stripline traces. Figure 6 shows the three traces as they appear on the board (not to scale). One of the traces (trace (c) of Figure 6) is straight; the other two contain one inch of straight trace, two inches of meandering, then three inches of straightaway (traces (a) and (b) in Figure 6). The actual board has three sets of the traces shown in Figure 6. Figure 7 shows a cross-section of the geometry used in the meandering sections of trace (a) and trace (b). Trace (a) used a 15-mil1 pitch (d=15 mils in Figure 7) and trace (b) used a 10-mil pitch (d=10 mils in Figure 7). The traces were 1/2-ounce copper, about 0.7 mils thick.

(a) (b) (c) Figure 6: Test Traces (One Set)

7 mils 1 d 2 3 4 3.3 mils 5 6 7 8 9 10

0.7 mil trace thickness 4 mils 1.4 mil return plane thickness

Figure 7: Cross-section of Meander Line Model

1. 1 mil = 0.001 inch = 0.0254 mm

6

The time-domain measurements were done with a Tektronix 11801 digital sampling oscilloscope. The input to the network was a voltage step of amplitude 250 mV and risetime 38 ps. The network analyzer used was an Agilent 8722ES. The test port power was -10dBm. 3.2 Time-Domain Transmission (TDT) Figure 8 shows the time-domain transmission results from the three sets of three test traces, superimposed. These are the waveforms seen at the output of each trace. The ?rst group of curves is for the 10-mil-pitch lines, the second for the 15-mil-pitch lines,and the third for the straight lines. The amplitude has been normalized with respect to the 250-mV step. The incident step happens at time 0. The delays are clearly different for the three line types (meandering with 10mil pitches, meandering with 15-mil pitches, and straight).

1 0.9 0.8 0.7

Normalized Amplitude

0.6 0.5 0.4 0.3 0.2

15-mil-pitch 10-mil-pitch

0.1 0 0.7

Straight

1 1.1 1.2 Time (ns) Figure 8: Time-Domain Transmission Results for Three Trace Types

0.8

0.9

7

3.3 Time-Domain Re?ectometry (TDR) Figure 9 shows a similar plot for the TDR results, where re?ection coef?cient has been converted into characteristic impedance. The incident step happens at time 0. The three sets of three traces are superimposed, but cannot be easily distinguished. There are no apparent correlations between line type and characteristic impedance. Each trace seems to have a characteristic impedance between about 55 ? and 65 ? , with no apparent pattern as to how impedance varies along the line.

70

65

Characteristic Impedance (Ohms)

60

55

50

45

40 ?1

0.5

0

0.5 Time (ns)

1

1.5

2

Figure 9: Re?ections Measured for Three Trace Types

8

0

0

5

1

10 ?2 ?15

| S11 | (dB)

| S21 | (dB)

8 9 10

3

20

4

25 ?5 ?30 ?6

35

40

7

10

10 Frequency (Hz)

10

10

8

10 Frequency (Hz)

9

10

10

150

150

100

100

S11 Phase (degrees)

50

S21 Phase (degrees)

8 9 10

50

0

0

50

50

100

100

150

150

8 9 10

10

10 Frequency (Hz)

10

10

10 Frequency (Hz)

10

Figure 10: S11 and S21 for Three Trace Types 3.4 Network Analysis Figure 10 presents S11 and S21 in magnitude and phase form for a straight trace, a 15-mil-pitch trace, and a 10-mil-pitch trace plotted together. Only one sample of each trace type is plotted in each chart.

4.0 Discussion of Results

The TDT picture of Figure 8 allows calculation of the time delays through each type of line. Clearly, the meandering lines are faster than a straight line of equivalent length. The trend is plotted in Figure 11. The horizontal axis of Figure 11 corresponds to the vertical axis of Figure 8: the fraction of full-scale voltage, or amplitude. For each amplitude level we have plotted the range of the differences in delay between each meander line and the straight line. For example, the 15mil-pitch lines led the straight line by 21-38 ps.

9

120

100

d=10 mils

Time delay reduction (ps)

80

60

40

d=15 mils

20

0 0

0.1

0.2

0.3

0.4 0.5 0.6 Normalized Amplitude

0.7

0.8

0.9

1

Figure 11: Time Delay Reduction Delay differs with the receiver??s threshold. Figure 11 shows how much time delay reduction, and variance in time delay, can be expected for a given logic threshold. For example, a receiver with a threshold of one-half the full-scale voltage will detect the delay for the 15-mil-pitch line as 30 ps shorter than the

delay for the straight line, and the delay for the 10-mil-pitch line is 50 ps shorter than the delay for the straight line. Therefore designers may think they have matched delays, but have actually created 50 ps of skew. The time delay reduction measurements are summarized in Table 1. Table 1: Time Delay Reduction d (mils) Straight 15 10 Nominal Meander Delay (ps) 340 340 340 Reduction (ps) 0 30 50 Error 0 9% 15%

The nominal meander delay was calculated by Equation 4-1, where Equation 2-2 has been used for velocity, and L refers to the intended length of the meandering section: L L 2in T nom = -- = = = 340 ps v 8m c? ?Å 3 ?Á 10 ? 4.3 s (4-1)

10

Figure 12: Meander Line Partitioned into Two Sets of Coupled Transmission Lines The TDR measurements of Figure 9 do not indicate a trend for the characteristic impedance that relates to the presence of a meander line. The variations from trace to trace caused by measurement or manufacturing errors dominate any meander-line effects. Also, the S-parameter graphs of Figure 10 do not show signi?cant differences. All three lines graphed have similar attenuation and re?ection characteristics.

5.0 Linked-W Element Circuit Model

A circuit model suitable for simulation in HSPICE has been developed which predicts the time delay reduction effect. This model is based on the observation that the center of Figure 12 looks like an array of wires running vertically. That array can be modelled as N coupled transmission lines with the HSPICE W element. In this section, we discuss how the model is constructed, present time-domain simulation results, and compare those results to the measured values. 5.1 Construction of Linked-W Model Each of the dashed rectangles contains a set of N parallel, lossy, coupled lines. Each rectangle can be replaced with a W element for simulation in HSPICE. Each W element will have 2N+1 terminals (two for each signal conductor segment and one for a ground reference). These terminals can be stitched together with ideal wires, and lumped capacitance can optionally be added at the turns.

11

Gnd

A1 1

Cturn

A2 3

Cturn

A3 5

Cturn

A4 7

Cturn

A5 9

Cturn

W element Gnd AB1

2

4

6

8

10

11 AB2

12 AB3

13 AB4

14 AB5

15 AB6

16 AB7

17 AB8

18 AB9

19

20

OUT IN W element Gnd 1 2 3 4 5 6 7 8 9 10

11 F1

12

13 F2

14

15 F3

16

17 F4

18

19 F5

20

Cturn

Cturn

Cturn

Cturn

Cturn

Gnd

Figure 13: Linked-W Circuit Model for Meander Section Figure 13 shows the circuit schematic used for this geometry. Each box is a 10-signal-conductor W element. A signal enters at terminal ??IN,?? crosses the lower W element on one of the signal conductors, then is fed into the neighboring signal conductor. Table 2 lists the parameters which must be speci?ed to construct the model [6]. In the rest of this section we will show how the value of each parameter was found or estimated. Table 2: Linked-W Model Parameters Parameter N L L matrix C matrix R matrix G matrix Rs matrix Cturn Description Number of parallel conductors Length of wire represented by each section Inductance