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Resistive switching characteristics of TiO2 films with embedded Co

14 JUN-HYUN BAE et al : A LOW-VOLTAGE HIGH-SPEED CMOS INVERTER-BASED DIGITAL DIFFERENTIAL TRANSMITTER WITH

    A Low-Voltage High-Speed CMOS Inverter-Based

    Digital Differential Transmitter with Impedance

    Matching Control and Mismatch Calibration

    Jun-Hyun Bae, Sang-Hune Park, Jae-Yoon Sim, and Hong-June Park

    AbstractA digital differential transmitter based on based digital differential transmitter. The two branches of CMOS inverter worked up to 2.8 Gbps at the supply inverter strings are used to implement the differential signal voltage of 1 V with a 0.18 m CMOS process. By driving path. This implementation is very simple and easy calibrating the output impedance of the transmitter, to change the process. However, when there are mismatches the impedance matching between the transmitter between the delays of the two inverter strings with the PVT output and the transmission line is achieved. The variations, the duty cycle and the common mode level PVT variations of pre-driver are compensated by the fluctuate with time [3,4]. The fluctuations of the duty cycle calibration of the rising-edge delay and falling-edge and the common mode level appear at the transmitter delay of the pre-driver outputs. The chip fabricated output as the delay mismatches of the rising-edge between with a 0.18 m CMOS process, which uses the standard two inverter strings and falling-edge of single inverter supply voltage of 1.8 V, gives the highest data rate of string. Also, because the output impedance of CMOS 4 Gbps at the supply voltage of 1.2 V. The proposed inverter-based output driver (DRV) can be easily varied with

    calibration schemes improve the eye opening with the the PVT variations, there can be the impedance mismatch voltage margin by 200% and the timing margin by between the output driver and the transmission line. These 30%, at 2.8 Gbps and 1 V. mismatches limit the maximum data rate that can be trans-

     mitted. Index TermsTransmitter, digital, differential, termi-In this work, the calibrations in the delay mismatches of nation, inverter-based, low voltage the two inverter strings are performed to increase the data

    rate of the differential signaling with a low supply voltage.

    Each inverter string consists of a pre-driver and a main driver. I. INTRODUCTION

    In the main driver, the termination calibration is performed

    to achieve the impedance matching between the main The differential signaling is widely used for high-speed

    driver and the transmission line. In the pre-driver, the cali-interface because of its superior immunity to environmental

    brations are done for the mismatches in the average delay noise and the low EMI. The digital circuits shrink rapidly

    and the duty cycle between the two inverter strings. The with the advent of recent semiconductor processes. Also

    the supply voltage is reduced to about 1 V for the state-of-

    the-art semiconductor processes. Efforts are driven to develop

    OUTthe CMOS inverter-based differential signaling schemes [1,2]. ZINDRV0Fig. 1 shows generally used conventional CMOS inverter-

    OUTBZINBDRV0Manuscript received xxx. x, 2009; revised xxx. x, 2009. Dep. EE., Pohang University of Science and Technology Pohang, Korea E-mail : baecha@postech.ac.kr Fig. 1. Conventional digital differential transmitter.

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.9, NO.1, MARCH, 2009 15

average delay calibration is done by aligning the rising-which has the information of the characteristic impedance.

    edge of the pre-driver output signal of one inverter string This termination impedance calibration is controlled by

    to that of the other inverter string. The duty cycle of the T_CAL.

    pre-driver output signal of each inverter string is calibrated PRE_DRV is the differential signal driving buffer which to 50% by adjusting the falling-edge of the pre-driver is based on CMOS inverter. The CMOS inverter is very

    output signal, respectively. sensitive to the PVT variations. Therefore, when low supply Section II shows the architecture of this work. Section voltage is used, the pull-up and pull-down driving strength

    III shows the circuit description. Section IV and V show of PRE_DRV is very sensitive to the PVT variations. The the measurement results and conclusion. driving strength mismatch between pull-up and pull-down

    can cause the delay mismatches. For the differential signal

    II. ARCHITECTURE path, the rising-edge delay mismatch induces a phase error

    between outputs of the two signal paths, and the falling-

    Fig. 2 shows the block diagram of the proposed digital edge delay mismatch induces a duty cycle error. Due to

    differential transmitter. There are five input signals - such these errors, the differential output signal of PRE_DRV cannot as, the differential input data (DIN and DINB), the clock maintain the signal information of the differential input [5],

    for pre-driver calibration (CLK), the pre-driver calibration and this can degrade the performance of the transmitter.

    control signal (PD_CAL), and the termination impedance To clear up these problems of the signal preservation, the

    calibration control signal (T_CAL). There are two output rising-edge delay mismatch between two signal paths of

    signals - such as the two output data (DOUT and DOUTB). PRE_DRV is calibrated by changing the PRE_DRV input The transmitter consists of, a pre-driver (PRE_DRV), an from the differential data to CLK. Then, the falling-edge main driver (DRV), two multiplexers, and an external delay of the each signal path is calibrated by changing the

    reference resistor (10Z). For the test of a fabricated chip, output duty cycle to 50%. These calibration operations eli-0

    minate the driving strength mismatch of the pull-up and there is a receiver with the split parallel termination. For

    the pull-down of PRE_DRV. the case of the split parallel termination, if the transmitter

    output impedance is properly matched to the characteristic

    impedance (Z) of the transmission line, the differential III. CIRCUIT DESCRIPTION 0

    voltage swing of the transmitter output is half the VTT.

    However, the impedance mismatch between DRV output 1. DRV with Termination Impedance Calibration

    and the transmission line brings about the signal reflection

    which reduces the voltage margin of the data eye. There-Fig. 3 shows the block diagram of DRV. There are four fore, the output impedance of DRV, which drives the di-input signals such as, differential input data (DIN and fferential data to the transmission line, must be the charac-DINB), external reference voltage (EXT_REF) which is teristic impedance (Zhalf the VTT, and termination impedance calibration ) of the transmission line. For this 0

    control signal (T_CAL). There are two output signals - impedance matching, the output impedance of DRV is

    such as the two output data (DOUT and DOUTB). calibrated to the Z by using the 10 times replica of the 0

    output driver and the external reference resistor (10Z), 010Z0

    CTRL_PU[5:0]VTTEXT_REFCTRL_PD[5:0]OUTTPUPD_CAL2Z0DINBDOUTZ0DIN0REF_PU2Z0OUTBCLK1TPDDRVPRE_DRVVTTDINDINB02Z0DOUTBTPU_CAL1Z0TPD_CALT_CTRL2Z0PD_CALT_CALPD_CALT_CAL10Z0TERMINATION CONTROLOUTPUT DRIVERTRANSMITTERRECEIVER

    Fig. 2. Block diagram of the proposed transmitter. Fig. 3. Block diagram of DRV.

    16 JUN-HYUN BAE et al : A LOW-VOLTAGE HIGH-SPEED CMOS INVERTER-BASED DIGITAL DIFFERENTIAL TRANSMITTER WITH

    characteristic impedance of the transmission line. Fig. 4 DRV consists of a pull-up termination circuit (TPU), a (c) shows digitally controlled resistor for the pull-down pull-down termination circuit (TPD), a termination calib-impedance matching. PD consists of seven NMOS ration controller (T_CTRL), and two main drivers. TPU switches and seven binary-weighted resistors. To prevent and TPD use the 10 times replica of the output driver. TPU the high impedance condition (no current path between generates 6-bit pull-up impedance control code (CTRL_ VSS and node B) of the pull-down signal path, one PU[5:0]) for the pull-up impedance matching by using ) and 10 times replica of NMOS switch is always turned on with the smallest 0external reference resistor (10Zthe pull-up part of the output driver. TPD generates 6-bit resistor among seven binary weighted resistors. According

    pull-down impedance control code (CTRL_PD[5:0]) for to the CTRL_PD[5:0], the impedance of PD is controlled the pull-down impedance matching by using 10 times to the characteristic impedance of the transmission line.

    replica of the output driver, CTRL_PU[5:0], and REF_PU. DRV drives the differential input signal which is buffered

    Fig. 4 (a) shows the circuit of the main driver. The main by PRE_DRV to the transmission line. Therefore, the output

    driver consists of a pull-up circuit (PU) and a pull-down impedance of DRV has to be matched to the characteristic

    circuit (PD) with the impedance control. The impedances impedance (Z) of the transmission line. First of all, for 0

    of PU and PD are controlled by the binary impedance this impedance matching, the pull-up impedance of DRV control codes (CTRL_PU[5:0] and CTRL_PD[5:0]) which is calibrated to Z by using TPU and the external reference 0

    are generated by the pull-up and pull-down termination resistor (10Z) that contains the information of the charac-0

    circuits (TPU and TPD). Fig. 4 (b) shows digitally controlled teristic impedance. Then, at TPD, the pull-down impedance resistor for the pull-up impedance matching. PU consists of DRV is calibrated to Z by using the calibrated pull-up 0of seven PMOS switches and seven binary-weighted resistors. impedance. T_CTRL controls the overall termination cali-To prevent the high impedance condition (no current path bration sequence by monitoring T_CAL, CTRL_PU[5:0], between VDD and node A) of the pull-up signal path, one CTRL_PD[5:0].

    PMOS switch is always turned on with the smallest resistor Fig. 5 (a) and Fig. 5 (b) show TPU and TPD, respect-among seven binary-weighted resistors. According to the tively. TPU consists of a replica 10 times the impedance

    CTRL_PU[5:0], the impedance of PU is controlled to the (PU_R) of pull-up part of the output driver, a comparator,

    and an up-down counter (UDC). TPD consists of the replica

    10 times of pull-up part (PU_R) of the output driver, a PUCTRL_PU[5:0]replica 10 times the impedance (PD_R) of pull-down part A

    INOUT

    BPDCTRL_PD[5:0]

    (a)

    CTRL_PU[0]CTRL_PU[5]

    (a) A

    CTRL_PU[5:0](b) PU_RREF_PUB+CTRL_PD[5:0]UDCREF_COM-

    CTRL_PU[0]CTRL_PU[5]TPD_CALPD_R

    (c) Fig. 4. (a) Circuit of output driver (b) Circuit of PU (c) Circuit (b) of PD. Fig. 5. Termination control circuits (a) TPU (b) TPD.

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.9, NO.1, MARCH, 2009 17

    of the output driver, the comparator, and UDC. DT_CAL

    +VDD/2In the TPU, the termination impedance calibration per-DTA_CTRL[4:0]FSM-LPFforms the calibrations of the pull-up impedance first. The

    voltage divided value (REF_PU) is generated by using the OUTBINPREAPREAPREAPREAexternal reference resistor (10Z) and PU_R. If REF_PU 0

    is the same as half VTT, the impedance of PU_R can be

    PDthe same as 10Z. So, by using half VTT as the EXT_REF, PH_CTRL[4:0]0FSMthe comparator compares REF_PU to EXT_REF. Then, PH_CALby using the comparison result of EXT_REF and REF_PU,

    UDC generates the pull-up impedance control code INBOUTPREBPREBPREBPREB(CTRL_PU[5:0]). Therefore, the negative feedback loop

    of PU_R, the comparator, and UDC can decide CTRL_PU +LPFFSMDTB_CTRL[4:0][5:0] which makes the voltage of REF_PU to half VTT; -VDD/2

    DT_CALthe impedance of PU_R to 10Z. 0

    (a) After the calibration of the pull-up impedance, the pull-

    down impedance control code (CTRL_PD[5:0]) is generated

    PU[0]PU[4]in the TPD. The voltage divided value (REF_COM) is

    generated by using the PD_R and previously calibrated

    PULL_UPPU_R. If REF_COM is the same as half VTT, the impe-

    dance of PD_R can be the same as the impedance of PU_R. INOUTBecause the pull-up impedance calibration is already PULL_DNfinished, the voltage of REF_PU is half VTT. So, by using

    REF_PU as the reference voltage, the comparator compares PD[0]PD[4]REF_COM to REF_PU. Then, by using the comparison

    result of the REF_PU and REF_COM, UDC generates the

    (b) pull-down impedance control code (CTRL_PD[5:0]). There-

    Fig. 6. (a) Block diagram of PRE_DRV (b) Circuit of PREA fore, the negative feedback loop of PD_R, the comparator,

    and PREB. and UDC can decide CTRL_PD[5:0] which makes the

     voltage of REF_COM to the half VTT; the impedance of

    PRE_DRV consists of two signal driving paths (IN to PD_R to 10Z. 0OUTB, and INB to OUT), a phase detector (PD), two The impedance of PU_R and PD_R is the 10 times

    comparators, two resistor-capacitor low-pass filters (LPF), replica of the pull-up and pull-down parts of the output

    and three finite-state machines (FSM). In case of the driver. Therefore, these impedance controls can calibrate

    signal path from IN to OUTB, the rising-edge delay is the output impedance of the output driver to the charac-

    fixed to certain value and the falling-edge delay is cont-teristic impedance (Z) of the transmission line. Therefore, 0rolled by the binary code (DTA_CTRL[4:0]). In case of the impedance matching between the transmission line the signal path from INB to OUT, the rising-edge and and the transmitter can be achieved. falling-edge delays are controlled by the binary codes, PH_CTRL[4:0] and DTB_CTRL[4:0], respectively. As 2. PRE_DRV with Mismatch Calibrations shown in Fig. 6 (b), PREA and PREB of PRE_DRV are the digitally controlled current starved delay element [6]. The Fig. 6 (a) shows the block diagram of PRE_DRV. There pull-up and pull-down parts of this circuit is controlled by are five input signals such as, differential input data (IN the binary control codes (PU[4:0] and PD[4:0]). To make and INB), phase error control signal (PH_CAL), duty cycle the fixed rising-edge delay of the signal driving path from error control signal (DT_CAL), and external reference IN to OUTB, the fixed binary code is applied to PU[4:0] voltage (VDD/2). There are two output signals - such as of PREA. the two pre-driver output data (OUT and OUTB).

18 JUN-HYUN BAE et al : A LOW-VOLTAGE HIGH-SPEED CMOS INVERTER-BASED DIGITAL DIFFERENTIAL TRANSMITTER WITH

    To calibrate the phase error between two signal driving error, the duty cycle errors of each signal driving path are paths and the duty cycle error of each signal driving path, still remained. Therefore, after the calibration of the phase there are one phase control loop and two duty cycle control control loop is finished, the duty cycle control loop is loops. The phase control loop consists of one signal driving activated. The duty cycle errors are caused by the devia-path (INB to OUT), PD, and FSM which is controlled by tion of the falling-edge delay. If the time difference bet-PH_CAL. The duty cycle control loop consists of one signal ween rising-edge and falling-edge is half period (T/2), the driving path, LPF, the comparator, and FSM which is duty cycle of pre-driver output is 50%. However, because controlled by DT_CAL. Fig. 7 shows the operation timing of the PVT variations, the falling-edge delay is varied. diagram of PRE_DRV. During PRE_DRV calibration, by This variation also distorts the EYE diagram of the pre-using two MUX (Fig. 2), the input of PRE_DRV is changed driver output and degrades transmitter performance. To from the differential input data to CLK which has the correct the duty cycle errors of each signal driving path, period of T. The PVT variations can cause mismatches in two duty cycle control loops are used. If the duty cycle of the PRE_DRV. As shown in the first timing diagram, if the pre-driver output is 50%, the averaged value of the there is no calibration scheme, two outputs of the PRE_DRV pre-driver output will be half VDD. Therefore, by com-has the phase error (PH. ERR.) between two outputs and paring the averaged value of the pre-driver output to half duty cycle errors (DT. ERR.) for each output. These errors VDD, each duty cycle control loop controls the falling-distort the EYE opening of the transmitter and degrade the edge delay to make the averaged value of the pre-driver transmitter performance. output to half VDD. As shown in the third figure of Fig. 7, The phase error between two outputs of the PRE_DRV the duty control loops can correct the duty cycle errors is caused by the mismatch of the rising-edge delays (DT. ERR.) of OUT and OUTB. Because two duty cycle

    between two signal driving paths. To correct the phase control loops control only the falling-edge delay of two error, the phase control loop operates as a general digital signal paths, the duty cycle control loops do not disturb delay-locked loop. The phase control loop compares the the calibrated rising-edge delay by the phase control loop. phase difference between OUT and OUTB, and controls Therefore, these delay controls can calibrate the phase the rising-edge delay of OUT to remove the phase error. error and the duty cycle errors which are caused by the The rising-edge delay of the signal path from IN to OUTB mismatches of PRE_DRV.

    is fixed. Therefore, as shown in the second timing diagram

    IV. MEASUREMENT RESULTS of Fig. 7, the phase control loop can remove the phase

    error. This phase control calibrates the rising-edge delay

    mismatch between two signal driving paths of PRE_DRV. The circuit was implemented by using 0.18 ?m CMOS

    Although the phase control loop removes the phase process. The chip, shown in Fig. 8, consists of the pro-

    posed digital differential transmitter and the receiver for

    PH. ERR.

    OUT

    OUTB

    DT. ERR.

    PHASE CONTROL

    DT. ERR.OUT

    OUTB

    DUTY CYCLE CONTROL

    T/2OUTT/2

    OUTB

    Fig. 7. Operation timing diagram of PRE_DRV calibration. Fig. 8. Chip layout.

    JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.9, NO.1, MARCH, 2009 19

    testing. The active chip area of the proposed transmitter is Voltage Margin Timing Margin250.0m300.0p480 ?m?700 ?m. The highest data rate of the fabricated

    chip was 4 Gbps at the supply voltage of 1.2 V. Fig. 9 shows 250.0p200.0m

    the measured differential output waveforms at the data 200.0p150.0mrate of 2.8 Gbps and the supply voltage of 1 V which is 150.0pTime [sec]about 2 times the threshold voltage. Fig. 9 (a) shows the 100.0m100.0pmeasured waveform for the case of turning-off the calib-50.0m50.0prations of both the termination impedance and PRE_DRV.

    0.00.0In this case, the eye diagram is distorted by the termina-No Cal.T_CALPD_CAL

    tion impedance mismatch and the phase error between two Fig. 10. Eye opening with the proposed calibrations.

    signal driving paths and the duty cycle errors of each

    Table 1. Performance summary (measurements). signal driving path of PRE_DRV. Fig. 9 (b) shows the

    Process 0.18 ?m CMOS

    Circuits Digital TX + RX for test

    Max. Speed 4Gbps @ 1.2 V

    Eye Opening @ 2.8 Gbps, 1 V

    No Calibration 8 0mV, 230 psec

    Term. Calibration 210 mV, 250 psec

    PRE_DRV Calibration 240 mV, 300 psec

    Power Consumption (TX) 30 mW @ 2.8 Gbps, 1 V

    Chip Area (TX) 480 ?m?700 ?m

    Voltage [V]measured waveform for the case of turning-on only the

    termination impedance calibration. By calibrating termi-

    nation impedance, the differential voltage swing is set to

    (a) VTT/2. Fig. 9 (c) shows the measured result of the calib-

    rations of both termination impedance and PRE_DRV.

    Fig. 10 shows the voltage margin and timing margin of

    the EYE diagram measured at the transmitter output. The

    termination calibration improved the voltage margin from

    80 mV to 210 mV and the timing margin from 230 psec to

    250 psec. The mismatch calibration improved the voltage

    margin from 210 mV to 240 mV and the timing margin from

    250 psec to 300 psec. As shown in the figure, the proposed

    calibration schemes improve the eye opening with the

    voltage margin by 200% and the timing margin by 30%. (b)

    Although the whole calibration sequence is finished,

    there is some distortion at the eye diagram of Fig. 9 (c).

    The distortion is caused by the short calibration range of

    the PRE_DRV calibration. By extending the calibration

    range, this signal distortion can be perfectly resolved.

    The measured performance is summarized in Table 1.

    V. CONCLUSIONS

    (c) A low-voltage CMOS digital differential transmitter

    was implemented with PVT mismatch calibration of pre-Fig. 9. Measured differential output waveforms @ 2.8Gbps and

    driver and impedance matching calibration of main driver. 1V (a) No calibration (b) DRV(termination) calibration (c)

    DRV calibration and PRE_DRV(mismatch) calibration. To reduce the reflection between the main driver and the

    20 JUN-HYUN BAE et al : A LOW-VOLTAGE HIGH-SPEED CMOS INVERTER-BASED DIGITAL DIFFERENTIAL TRANSMITTER WITH

    Jun Hyun Bae was born in Ui-Seong, transmission line, the output impedance of the main driver

    Korea, on 1981. He received the B.S. was calibrated to the characteristic impedance of the

    degree in the Department of Electronic transmission line by using external reference resistor. By

    and Electrical Engineering from calibrating the pull-up and pull-down driving strength of

    Kyung-Pook National University, the pre-driver, the differential signal distortion of the pre-

    Korea, in 2004 and M.S. degree in driver output, which is sensitive to PVT variations, is

    Electronic Engineering from Pohang compensated. The chip was fabricated with 0.18 ?m CMOS

    University of Science and Technology (POSTECH), Korea, process which uses the standard supply voltage of 1.8 V.

    in 2007, respectively. He is currently pursuing the Ph.D. The highest data rate was 4 Gbps at 1.2 V. The calibration

    degree in the Department of Electronic and Electrical schemes improved the output eye opening with the vol-

    Engineering from Pohang University of Science and tage margin of 200% and the timing margin of 30%, at 2.8 Technology (POSTECH), Korea. His interests include data Gbps and 1 V.

    converters, high-speed interface circuits and ultra-low-

    voltage analog circuits. ACKNOWLEDGMENTS

    This work was supported by IDEC, and BK21 program,

    KOREA.

    REFERENCES Sang-Hune Park received the B.S.,

    M.S., Ph.D. degrees in the Department [1] R. Palmer, et al, A 14 mW 6.25 Gb/s Transceiver of Electrical Engineering from Pohang in 90 nm CMOS for Serial Chip-to-Chip Communi-University of Science and Technology, cations, Solid-State Circuits Conference, 2007. ISSCC Pohang, Korea, in 2000, 2002, and 2007. Digest of Technical Papers. IEEE International, 2008, respectively. In 2008, he joined 11-15, Feb. 2007, pp. 440-614. at Samsung Electronics, where he has [2] K.-L.J. Wong, et al, A 27-mW 3.6-gb/s I/O tran-been working in the area of high-speed interface circuit sceiver, Solid-State Circuits, IEEE Journal of, vol. design. His interests include high speed CMOS circuit 39, Issue 4, April 2004, pp.602-612. design and digital mixed-signal ICs. [3] Y. C. Jang, J. H. Bae, and H. J. Park, “A Digital CMOS PWCL With Fixed-Delay Rising Edge and Digital Stability Control, Circuits and Systems II, IEEE Transactions on, vol. 53, Issue 10, Oct. 2006, pp.1063-1067. Jae-Yoon Sim received the B.S., M.S., [4] Peng Xu and P. Abshire, “Stochastic Behavior of a and Ph.D. degrees in Electronic and CMOS Inverter,Electronics, Circuits and Systems, Electrical Engineering from Pohang 2007, ICECS 2007, 14th IEEE International Con-University of Science and Technology, ference on, 11-14 Dec. 2007, pp.94-97. Korea, in 1993, 1995, and 1999, res- [5] L. Bisdounis, S. Nikolaidis, and O. Loufopavlou, pectively. From 1999 to 2005, he was Propagation delay and short-circuit power dissi-

    a Senior Engineer at Samsung Elec-pation modeling of the CMOS inverter,Circuits

    tronics, Korea. From 2003, to 2005, he was a post-doctoral and Systems I: Fundamental Theory and Applica-

    student with the University of Southern California, Los tions, IEEE Transactions on, vol. 45, Issue 3, March

    Angeles. In 2005, he joined the Faculty of Electronic and 1998, pp.259-270.

    Electrical Engineering, Pohang University of Science and [6] M. Maymandi-Nejad and M. Sachdev, A monotonic

    Technology, Korea, where he is currently an Assistant digitally controlled delay element,Solid-State Cir-

    Professor. His research interests include PLL/DLL, high-cuits, IEEE Journal of, vol. 40, Issue 11, Nov. 2005,

    speed links, memory circuits, and ultra low-power analog. pp.2212-2219.

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.9, NO.1, MARCH, 2009 21

    Hong June Park received the B.S.

    degree from the Department of Elec-

    tronic Engineering, Seoul National

    University, Seoul, Korea, in 1979, the

    M.S. degree from the Korea Advanced

    Institute of Science and Technology,

    Taejon, in 1981, and the Ph.D. degree from the Department of Electrical Engineering and Com-

    puter Sciences, University of California, Berkeley, in 1989.

    He was a CAD engineer with ETRI, Korea, from 1981 to

    1984 and a Senior Engineer in the TCAD Department of

    Intel from 1989 to 1991. In 1991, he joined the Faculty of

    Electronic and Electrical Engineering, Pohang University

    of Science and Technology (POSTECH), Kyungbuk,

    Korea, where he is currently Professor. His research interests

    include high-speed CMOS interface circuit design, signal

    integrity, device and interconnect modeling. Prof. Park is

    a member of IEEK, IEEE and IEICE.

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