LECC 2002 – Colmar Workshop
0.25？m Rad-Hard chip for ALICE ITS data acquisition 1 - Realization and test of a
Davide Falchieri, Alessandro Gabrielli, Enzo Gandolfi
email@example.com ; firstname.lastname@example.org
Viale Berti Pichat 6/2 40127 Bologna Italy
CARLOS2 is a second version of a chip that is part of the data acquisition chain for the ALICE ITS experiment. The first version of the chip has been implemented on Alcatel 0.35？m CMOS digital technology and included 8 8-bit channels. Conversely this second version deals just with two 8-bit channels to increase fault-tolerance during future tests and actual data acquisition. Moreover this version has been implemented using the CERN developed digital library of enclosed gate transistors. This is a rad-hard library developed within RD49 project. The prototype works well and it is going to be applied for ALICE ITS 2002 test beams.
The paper explains the design and the realization of a small size digital Rad-Hard chip submitted at CERN multi-project run Multi-Project-Wafer-6 in November 2001. The design is a part of the Large Hadron Collider (LHC) A Large Ion Collider Experiment (ALICE) experiment at CERN and, particularly, is a device oriented to a electronic front-end board for the Inner Tracking System (ITS) data acquisition. The chip has been designed in VHDL language and implemented in 0.25？m CMOS 3-metal Rad-Hard
CERN v1.0.2 digital library. It is composed of 10k gates, 84 I/O pads out of the 100 total 2pads, it is clocked at 40MHz, it is pad-limited and the whole die area is 4x4 mm.
The system requirements for the Silicon Drift Detector (SDD) readout system derive from both the features of the detector and the ALICE experiment in general. The amount of data generated by the SDD is very large: each half detector has 256 anodes and for each anode 256 time samples have to be taken in order to cover the full drift length. The data outgoing from two half detectors are read by one 2-channel CARLOS2 chip. The electronics is inserted on a board in a radiation environment. The whole acquisition system electronics performs analog data acquisition, A/D conversion, buffering, data compression and interfacing to the ALICE data acquisition system. The data compression and interfacing task is carried out by CARLOS2 chip. Each chip reads two 8-bit input data, is synchronized with an external trigger device and writes a 16-bit output word at 40MHz. Indeed, CARLOS2 mainly contains a simple encoding for each channel and the data are packed into a 15-bit barrel-shifter. Then a further bit is added to indicate if the
LECC 2002 – Colmar Workshop
data are dummy or actual: this leads to a 16-bit output data. After this electronics the data are serialised and transmitted by means of an optical link at 800Mbit/s. CARLOS2 will then be used to acquire data in the test beams and will allow us to build and test the foreseen readout architecture.
The chip has been sent to the foundry in November 2001 and have been tested starting from February 2002. A specific PCB has been designed for the test task; it contains the connectors for probing the ASIC with a pattern generator and a logic state analyser. The chip is inserted on the PCB using a ZIF socket. This allows us to test the 20 packaged samples out of the total amount of bare chips we have from the foundry. The test phase has shown that 12 out of 20 chips under test work well. Nevertheless it is planned to redesign a new version of the chip by adding extra features. This will not substantially increase the chip area since it is pad-limited and should be close to the final version of the chip for the ALICE ITS experiment.
2 - The Clock and Control Board for the Cathode Strip Chamber Trigger and DAQ Electronics at the CMS Experiment
M. Matveev , P. Padley
Houston, TX 77005
The design and functionality of the Clock and Control Board (CCB) for the Cathode Strip Chamber (CSC) peripheral electronics and Track Finder crate at the CMS experiment are described. The CCB performs interface functions between the Timing, Trigger and Control (TTC) system of the experiment and the CSC electronics.
The CSC electronic system consists of on-chamber mounted front end anode and cathode boards, electronics on the periphery of the detector, and a Track Finder in the counting room. The Trigger/DAQ electronic system resides in 60 VME crates located on the periphery of the return yoke of the CMS detector and includes: the combined Cathode LCT/Trigger Motherboards, the Data Acquisition Motherboards, the Muon Port Card and the CCB. The Track Finder consists of a number of Sector Processors, Muon Sorter and CCB, all residing in a single crate in the underground counting room.
All elements of the CSC electronics should be synchronized with the LHC. The TTC system is based on an optical fan-out system and provides the distribution of the LHC
LECC 2002 – Colmar Workshop
timing reference signal, the first level trigger decisions and its associated bunch and event numbers from one source to about 1000 destinations. The TTC system also allows to adjust the timing of these signals. At the lowest levels of the TTC system, the TTCrx ASIC receives control and synchronization information from the central TTC system through the optical cable and outputs TTL-compatible signals in parallel form.
The CCB is built as a 9U*400 mm VME board that comprises a mezzanine card with a TTCrx ASIC produced at CERN and a second mezzanine card with a PLD to reformat TTC signals for use in the crate. All communications with other electronics modules are implemented over a custom backplane. The CCB can also simulate all the TTC signals under VME control. In addition, various timing and control signals (such as 40.08 Mhz clock, L1 Accept etc) can be transmitted through the front panel. This option provides great flexibility for various testing modes at the final assembly and testing sites where
. hundreds of the CSC chambers will be tested before installation at the experimental hall
3 - Design and performance testing of the Read Out Boards for CMS-DT chambers
C. Fernández, J. Alberdi, J. Marin, J.C. Oller, C. Willmott
Cristina Fernández Bedoya
Readout boards (ROB) are one of the key elements of readout system for CMS barrel muon drift chambers. To insure proper and reliable operation under all detector environmental conditions an exhaustive set of tests have been developed and performed on the 30 pre-series ROB's before production starts.
These tests include operation under CMS radiation conditions to detect and estimate SEU rates, validation with real chamber signals and trigger rates, studies of time resolution and linearity, crosstalk analysis, track pattern generation for calibration and on-line tests, and temperature cycling to uncover marginal conditions. We present the status of the readout boards (ROB) and tests results.
Within the readout system, ROB's receive and digitize up to 128 differential signals from the Front-End electronics. They are built around a TDC (HPTDC) developed by CERN/EP Microelectronics group with a time bin resolution of 0.78 ns. Inside HPTDC a trigger matching is performed at arrival of every L1A, with the ability to handle overlapping trigger, i.e., triggers separated by less than a drift time. Timing and positional basic information is then routed through a multiplexer (ROS-Master) to DDU and Readout Unit at CMS TriDAS, for muon track reconstruction.
LECC 2002 – Colmar Workshop
Each ROB has 4 HPTDC's in a ring, where one of them is programmed as master to control the token read-out data_ready/get_data handshake protocol, and is controlled through a readout chamber bus for set-up, monitoring, and trigger and timing control. Translated level input signal are also lead to DT trigger logic, and output data are driven into an LVDS link serializer.
With the aim of checking ROB design and to define and develop production acceptance tests a set of test jigs have been built. Appropriate hardware and software was built to perform exhaustive ROB testing for monitoring, controlling and data acquisition. With this set-up, irradiation tests have been made with 60 MeV protons at UCL. Results show that the single event upset rate would be below 1 per day in the whole detector. Moreover, two test beams have validated HPTDC operation and ROB design under real chamber conditions. The readout system was placed with a chamber at CERN Gamma Irradiation Facility (GIF) and operated under two different beam conditions, one of them with a 25ns bunched structure. We could prove that the system can stand high hit rates, as well as noisy channels, and overlapping triggers.
Other parameters have also been measured, like resolution, linearity, and crosstalk. The later by studying the influence in the time measurement of one single channel by neighbour channel signals, with very good results, as this influence is in all cases below half the time bin resolution.
Besides that, ROB has been exposed to 0ºC to 70ºC temperature cycles showing small time measurement variations, and also proper ROB operation under diverse environmental conditions. The time shift estimated from these tests is about 15ps/ºC, which is absolutely acceptable.
In conclusion, the whole ROB functionality has been tested with very satisfactory results. The ROB design has been validated, being ready for final production.
4 - The ATLAS Level-1 Muon to Central Trigger Processor Interface (MUCTPI)
N. Ellis, P. Farthouat, K. Nagano, G. Schuler, C. Schwick, R. Spiwoks, T. Wengler
The Level-1 Muon to Central Trigger Processor Interface (MUCTPI) receives trigger information synchronously with the 40 MHz LHC clock from all trigger sectors of the muon trigger. The MUCTPI combines the information and calculates total multiplicity values for each of six programmable pT thresholds. It avoids double counting of single muons by taking into account the fact that some muons cross more than one sector. The MUCTPI sends the multiplicity values to the Central Trigger Processor which takes the final Level-1 decision. For every Level-1 Accept the MUCTPI also sends region-of-interest information to the Level-2 trigger and event data to the data acquisition system. Results will be presented on the functionality and performance of a demonstrator of the MUCTPI in full-system stand-alone tests and in several integration tests with other elements of the trigger and data acquisition system. Lessons learned from the demonstrator will be discussed along with plans for the final system.
LECC 2002 – Colmar Workshop
5 - ATLAS Tile Calorimeter Digitizer-to-Slink Interface
K. Anderson, A. Gupta, J. Pilcher, H. Sanders, F. Tang, R. Teuscher, H. Wu
The University of Chicago
This paper describes the ATLAS Tile Calorimeter Digitizer-to- Slink interface card design, performance and radiation hardness tests and production processes.
A total of about 10,000 channels of a readout system are required for Tile Calorimeter, which are housed in 256 electronics drawers. Each electronics drawer in Tile Calorimeter has one interface card. It receives optical TTC information and distributes command and clock signals to 8 digitizer boards via LVDS bus lines. In addition, it collects data from 8 digitizer boards in a format of 32-bit word at a rate of 40Mbps. The data of each drawer is aligned, repacked with headers and CRC control fields. It is then subsequently serialized with G-link protocol to be sent out to ROD module via a dual optical G-link at a rate of 640Mbps. The interface card can order the sequence of output channels according to drawer geometry or tower geometry. A master clock can be selected for timing adjustment, either from an on-board clock or from one of the eight DMU clocks to eliminate effects of propagation time delays along the data bus from each digitizer boards.
Since each interface card transports data from an entire electronics drawer, any failure could cause all data loss of an entire drawer. To overcome this hazard, we have incorporated a 2-fold redundant circuit design including optical components. An on-board failure detection circuits automatically selects one of the two TTC receivers. Other redundant functional circuits work in parallel. The destination ROD module makes a decision to take the data from one of two channels based on data qualities and failure conditions.
- High Voltage Power Supply Module Operating in Magnetic Field 6
University of Tokyo
Bunkyo-ku, Tokyo 113-0033
Tel: +81 3 3815 8384
Fax: +81 3 3814 8806
LECC 2002 – Colmar Workshop
The article describes a high voltage power supply module which can work efficiently under a magnetic field of 1.5 tesla. The module incorporates a piezoelectric ceramic transformer. The module includes feedback to stabilize the output voltage, supplying from 2000V to 4000V to a load of more than 10 megohm at an efficiency of higher than 60 percent. The module provides interface so that a micro-controller chip can control the module. The chip can set the output high voltage, detects the short circuit of the output high voltage and control its recovery. The chip can also monitor the output current. Most functions of the module are brought under the control of the chip. The module will be soon commercially available from a Japanese manufacturer.
High Voltage Power Supply Module Operating in Magnetic Field (M. Imori, H. Matsumoto, H. Fuke, Y. Shikaze and T. Taniguchi) High Voltage Power Supply Module The article describes a high voltage power supply module. The module includes feedback to stabilize the output voltage, supplying from 2000V to 4000V to a load of more than 10 megohm at efficiency of higher than 60 percent. The module incorporates a ceramic transformer. So the module can be operated efficiently under a magnetic field of 1.5 tesla. The module could be utilized in LHC experiments. The module will be soon commercially available from a Japanese manufacturer
The output voltage is fed to the error amplifier to be compared with a reference voltage. The output of the error amplifier is supplied to a voltage-controlled oscillator (VCO), which generates the driving frequency of the carrier supplied to the ceramic transformer. Voltage amplification of the transformer depends on the driving frequency. The dependence is utilized to stabilize the output voltage. The amplification is adjusted by controlling the driving frequency.
Breakdown of Feedback
While the load of the power supply falls within an allowable range, the driving frequency is maintained higher than the resonance frequency of the transformer such that the
feedback is negative as designed. The allowable range of load cannot cover, for example, short-circuiting the output voltage to ground. When the load deviates beyond the allowable range, the driving frequency may decrease below the resonance frequency; a condition that will not provide the required negative feedback, i.e., positive feedback locks the circuit such that it is independent of load.
Interface to Micro-controller Chip
The module provides interface so that a micro-controller chip can control the module. Most functions of the module are brought under the control of the chip.
Output High Voltage
A reference voltage is generated by a digital-to-analog converter kept under the control of the chip. So the output voltage can be set by the chip.
Recovery from Feedback Breakdown
LECC 2002 – Colmar Workshop
A VCO voltage, being the output of the error amplifier, controls the driving frequency. The feedback breakdown is produced by deviation of the VCO voltage from its normal range. The deviation, detected by voltage comparators, interrupts the chip. Then, the chip outputs a report of feedback breakdown and controls the module so as to recover from the breakdown.
If both the output high voltage and the supply voltage are known before hand, the driving frequency at which the transformer is driven depends on the magnitude of the load. The output current can be estimated from the driving frequency. The chip gets the driving frequency by counting pulses, which allows coarse estimation of the output current.
Y. Shikaze, M. Imori, H. Fuke, H. Matsumoto and T. Taniguchi,
A High-Voltage Power Supply Operating under a Magnetic Field,
IEEE Transactions on Nuclear Science, Vol. 48, June, 2001,
M. Imori, T. Taniguchi and H. Matsumoto,
Performance of a Photomultiplier High-Voltage Power Supply Incorporating a Piezoelectric Ceramic Transformer,
IEEE Transactions on Nuclear Science, Vol. 47, Dec. 2000,
M. Imori, T. Taniguchi, and H. Matsumoto,
A Photomultiplier High-Voltage Power Supply Incorporating a Ceramic Transformer Driven by Frequency Modulation,
IEEE Transactions on Nuclear Science, Vol. 45, June 1998,
M. Imori, T. Taniguchi, H. Matsumoto and T. Sakai,
A Photomultiplier High-Voltage Power Supply Incorporating a Piezoelectric Ceramic Transformer,
IEEE Transactions on Nuclear Science, Vol. 43, June, 1996,
7 - TESTS OF CMS REGIONAL CALORIMETER TRIGGER PROTOTYPES
P. Chumney, S. Dasu, M. Jaworski, J. Lackey, P. Robl, W.H. Smith
University of Wisconsin – Madison
Wesley H. Smith
University of Wisconsin Physics Department
1150 University Ave. Madison, Wisconsin 53706 USA
tel: (608)262-4690, fax: (608)263-0800,
LECC 2002 – Colmar Workshop
The CMS regional calorimeter trigger system detects signatures of electrons/photons, taus, jets, and missing and total transverse energy in a deadtimeless pipelined architecture. It uses a Receiver Card, with four gigabit copper cable receiver/deserializers on mezzanine cards, that deskews, linearizes, sums and transmits data on a 160 MHz backplane to an electron isolation card which identifies electrons and a jet/summary card that sums energies. Most of the processing is done on five high-speed custom ASICs. Results from testing the prototypes of this system, including serial link bit error rates, data synchronization and throughput measurements, and ASIC evaluation will be presented.
The CMS Regional Calorimeter Trigger (RCT) electronics comprises 18 crates for the barrel, endcap, and forward calorimeters and one cluster crate to handle the jet algorithms. Each crate contains seven rear mounted Receiver Cards (RC), seven front mounted Electron Isolation cards (EIC), and one front mounted Jet Summary (J/S) card plugged into a custom point-to-point 160 MHz differential ECL backplane. Each crate outputs the sum Et, missing energy vector, four highest-ranked isolated and non-isolated electrons, and four highest energy jets and four tau-tagged jets along with their locations.
Twenty-four bits comprising two 8-bit compressed data words of calorimeter energy, an energy characterization bit, and 5 bits of error detection code are sent from the ECAL, HCAL, and HF calorimeter electronics to nearby RCT racks on 1.2 Gbaud copper links. This is done using one of the four 24-bit channels of the Vitesse 7216-1 serial transceiver for 8 channels of calorimeter data per chip. The V7216-1 chips mounted on eight mezzanine cards on each RC deserialize the data, which is then deskewed, linearized, and summed before transmission on a 160 MHz custom backplane to 7 EIC and one J/S. The J/S sends the regional Et sums to the cluster crate and the electron candidates to the global calorimeter trigger (GCT). The cluster crate implements the jet algorithms and forwards 12 jets to the GCT.
The RC also shares data on cables between RCT crates. The RC Phase ASICs align and synchronize the four channels of parallel data from the Vitesse 7216-1, as well as checking for data transmission errors. Lookup tables are used to translate the incoming Et values onto several scales and set bits for Minimum Ionizing and Quiet signals. The Adder ASICs sum up eight 11-bit energies (including the sign) in 25 ns, while providing bits for overflows. The Boundary Scan ASIC handles board level boundary scan functions and drivers for the backplane. Four 7-bit electromagnetic energies, a veto bit, and nearest-neighbor energies are handled every 6.25 ns by the Isolation ASICs, which are located on the electron isolation card. Four electron candidates are transmitted via the backplane to the jet/summary (J/S) card. Sort ASICs are located on the jet/summary cards for sorting the e/g and processing the Et sums.
LECC 2002 – Colmar Workshop
All 5 of the ASICs were produced in Vitesse FXTM and GLXTM gate arrays utilizing their sub-micron high integration Gallium Arsenide MESFET technology. Except for the 120 MHz TTL input of the Phase ASIC, all ASIC I/O is 160 MHz ECL.
A custom prototype 9U VME crate, clock and control card, RC, and EIC have been produced along with the above 5 ASICs. Mezzanine cards with the Vitesse 7216-1 serial link for the RC and dedicated detailed test cards for these Mezzanine Cards have also been constructed. Results from testing, including the bit error rate of the Vitesse 7216-1 4-Gbaud Cu Links, data synchronization and throughput measurements, and ASIC evaluation will be presented.
8 - A flexible stand-alone testbench for characterizing the front-end electronics for the CMS Preshower detector under LHC-like timing conditions
A flexible test system for simulating LHC-like timing conditions for evaluating the CMS Preshower front-end electronics (PACE-II, designed in DMILL 0.8micron BiCMOS) has been built using off-the-shelf components. The system incorporates a microcontroller and an FPGA, and is controlled via a standard RS232 link by a PC running LabView. The system has been used to measure the digital functionality and analogue performance, including timing, noise and dynamic range, on about 100 PACE-II samples. The system has also been used in a beam test of Preshower silicon sensors, and may be viewed as a prototype for the final evaluation system of ~5000 PACE.
Samples of the radiation-tolerant front-end electronics for the CMS Preshower detector (PACE-II, designed in DMILL 0.8micron BiCMOS) have been extensively tested using a programmable system utilizing off-the-shelf components. The PACE-II comprises two separate chips: the Delta (32-channel pre-amp + switched-gain shaper, with programmable electronic injection pulse for calibration purposes) and the PACE-AM (32-channel, 160-cell analogue memory with 20MHz multiplexed output of three time-samples per channel per trigger). These two chips are mounted on a PCB hybrid and bonded together. The hybrids plug-in to a motherboard containing an ADC, an FPGA and a microcontroller. The FPGA (Altera FLEX 10k) provides fast timing (40MHz clock) and control signals for the PACE-II, including programmable bursts oftriggers, and allows us to simulate the conditions that we will experience in the LHC. The microcontroller (Mitsubishi M16C) is used to control the FPGA, provide slow control signals to the PACE-II (via an on-board I2C interface) and acquires digital data from the ADC and stores them in a FIFO before sending them, upon request, via a standard RS232 serial link to a PC running LabView. The motherboard also contains programmable
LECC 2002 – Colmar Workshop
delay-lines for accurate positioning of the ADC clock and the trigger sent to the PACE-II. As all components of the test-setup are completely programmable, the variety of tests that we are able to perform has evolved from sending simple digital functionality sequences (using an oscilloscope to monitor the output) to a fully-fledged data-acquisition system that has been used during beam tests of real Preshower silicon sensors bonded to the Delta chips. The tests that we can now perform, in order to evaluate the functionality and performance of a PACE-II, include the following:
.Programming and verification of registers, via I2C, on the Delta and PACE-AM chips
.Scan mode (feature for screening of fabrication defects in the logic parts of PACE)
.Injection test for each of the 32 channels, using the electronic calibration pulse in the Delta chip
.Dynamic range etc.: the amplitude of the calibration signal is
programmable (DAC on the Delta), allowing the gain, dynamic range and linearity of specified channels to be measured
.Timing scan: delaying the trigger signal by a certain amount, in steps of 0.25ns,
allows us to reconstruct the pulse-shape output by the Delta and thus measure the peaking-time etc.
.Pedestals/noise: we can study the pedestal uniformity of the memory and the single-cell noise for all channels (allowing signal-to-noise evaluation)
The system has allowed us to perform a detailed systematic evaluation of ~100 hybrids in order to determine our yield, verify the functionality and performance of PACE-II, both before and after irradiation, and study chip-to-chip uniformity.
The simplicity and flexibility of the setup means that it may be viewed as a prototype for a quality control/assurance system to be used to evaluate the full production of about 5000 PACE-II chips.
9 - Production Testing of ATLAS Muon ASDs
John Oliver, Matthew Nudell : Harvard University
Eric Hazen, Christoph Posch : Boston University
A production test facility for testing up to sixty thousand octal
Amp/Shaper/Discriminator chips (MDT-ASDs) for the ATLAS Muon Precision
Chambers will be presented. These devices, packaged in 64 pin TQFPs, are to be mounted onto 24 channel front end cards residing directly on the chambers. High expected yield and low packaging cost indicates that wafer level testing is unnecessary. Packaged devices will be tested on a compact, FPGA based Chip Tester built specifically for this chip. The Chip Tester will perform DC measurements, digital i/o functional test, and dynamic tests on each MDT-ASD in just a few seconds per device. Functionality and architecture of this Chip Tester will be described.