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EE 397K COMPUTER PERFORMANCE EVALUATION AND BENCHMARKING

By Bobby Adams,2014-04-15 05:53
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Review of basic logic design techniques (emphasis on timing); Design Flow, High level design; VHDL description of digital systems and simulation; Synthesis

    EE 360M DIGITAL SYSTEM DESIGN USING VHDL

    Spring 2007 ENS 302 T-Th 11:00 12:30pm Unique 16110

Instructor: Dr. Lizy Kurian John

    Office: ACES 3.114

    Office Phone: 232-1455

    Office Hours: T W Th 9:30-10:30am

    e-mail: ljohn@ece.utexas.edu

TAs:

    Karthik Ganesan, karthik@mail.utexas.edu

    Nidhi Nayyar, nidhin@mail.utexas.edu

    TA hours: TBD

Grader: Sreenivasan Padmanabhan, sreenivasan@mail.utexas.edu

    If you have grading questions, ask directly to the TA/grader by email.

Slides URL: http://www.ece.utexas.edu/~ljohn/ee360mslides

    Course Description: In this course, the principles of advanced digital design will be taught. It builds on logic design principles learned in EE316 and demonstrates how digital design and rapid

    prototyping have been facilitated by FPGAs and hardware description languages. It has a lab

    component involving VHDL and FPGAs.

Prerequisites: EE 316 and EE319K with a grade of at least C in each.

TextBook: C. H. Roth and L. K. John, Digital System Design Using VHDL, Second edition

    Available from HKN as a course packet. This packet is required for the course.

Grading Policy:

Lab assignments, Homeworks 25%

    Midterm Exams 50%

    Final Exam 25%

    Class Participation, Optional HWs, Pop quizzes 5% (optional)

    (Tests will count 70% with this option.)

Course contents:

    ? Review of basic logic design techniques (emphasis on timing)

    ? Design Flow, High level design

    ? VHDL description of digital systems and simulation

    ? Synthesis

    ? Design using Programmable logic devices

    ? SM Charts

    ? Field Programmable Gate Arrays (FPGAs)

    ? Advanced Topics in VHDL

    ? Test generation and design for testability

    ? Rapid Prototyping using FPGAs

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Lab: The course has a lab component (VHDL and FPGAs). The primary lab is ENS308. Lab

    involves VHDL simulation, VHDL Synthesis and Designing on FPGAs. Computers in ENS 317,

    ENS 340, and ENS 507 can also be used for simulation. Software packages for logic design,

    digital system simulation, gate array design, VHDL etc will be available in all labs, however,

    hardware FPGA boards are available only in ENS 308. You can access the lab using your new

    badge with the proximity chip.

The lab assignments and project are an important part of the course. Your course grade will be

    no better than the lab grade. i.e. if you have an overall A, but your lab grade is only a C, you

    will only get a C in the course.

The lab assignments will generally be due at 6pm in the lab. Extra credit of 1% can be earned by

    turning in 24 hours early and extra credit of 2% can be earned by turning in 2 days early.

    Assignments will be accepted late with 10% credit loss per day for 3 more working days after the

    due date. No credit for assignments turned in after that. There will be a few paper and pencil

    homework assignments. Due dates for them will be announced with each assignment. Weekend is

    treated as one day.

There will be 3 tests during the semester and a comprehensive final. All tests count equally. The

    lowest test score will be dropped. If you have more than 80% on each of the first 3 tests and you

    are happy with your course grade before the finals, you can choose to not take the final. But you

    should give a written request to me, on the prescribed form (to be made available), before the last

    class day.

    Pop quizzes: You have the option of using attendance, optional paper and pencil homeworks, pop quizzes and class participation towards 5% of the grade. (Test grades will count 70% instead

    of 75% in that case.) There will be pop quizzes and worksheets every now and then. I will drop

    10% of quizzes. No makeups allowed on pop quizzes.

Dishonesty in any work related to the course will be treated very seriously. No proxies allowed

    for pop quizzes or any other graded work. For homework and lab assignments, while discussing

    with other students is allowed, do not look at other students’ written solutions or VHDL code. Do not leave your directories/disks accessible to others.

Cell phones should be turned off before the class starts. If your cell phone rings in class, you will

    lose credit equivalent to one pop quiz. If my phone rings, you will get free credit for 1 quiz.

The first lab assignment is individual. For subsequent lab assignments, you will work with a

    partner. Working in teams is an important part of being an engineer. Please form teams of 2. If

    you are unable to find a partner, we will assign you one. The lab partners have to contribute

    equally to the assignment, but the lead member with the primary responsibility of demo’ing will

    alternate for each assignment. Both members should be present for the demo, but if for any reason,

    one cannot, the lead member is not allowed to be absent. You have the option of picking team

    members whose schedules suit yours. Start working on it now itself. If a team member does not

    contribute to an assignment, the TAs and I need to be informed at the demo of that lab. No

    credit for non-participating team members. Do not come at the end of the semester saying your

    team partner did not help.

Please check the course web page periodically for any last minute announcements. I’ll be sending

    announcements to the email list and if appropriate, leave a copy of the announcement on the web

    page.

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    The labs are NOT equally weighed. The last 2 lab assignments are worth twice/thrice as some of the early lab assignments.

    Please keep your solution sheets neat, clean and organized. That will enable the TAs/instructor to understand your solution and give you appropriate credit. Being illegible will reduce your credit. Write your name legibly on all your work.

No disruptive activity/talking in class during lectures. If you have a question on the material,

    ask the instructor. Be professional in your behavior in class.

    Academic Dishonesty

    Faculty in the ECE Department are committed to detecting and responding to all instances of scholastic dishonesty and will pursue cases of scholastic dishonesty in accordance with university policy. Scholastic dishonesty, in all its forms, is a blight on our entire academic community. All parties in our community -- faculty, staff, and students -- are responsible for creating an environment that educates outstanding engineers, and this goal entails excellence in technical skills, self-giving citizenry, and ethical integrity. Industry wants engineers who are competent and fully trustworthy, and both qualities must be developed day by day throughout an entire lifetime. Scholastic dishonesty includes, but is not limited to, cheating, plagiarism, collusion, falsifying academic records, or any act designed to give an unfair academic advantage to the student. The fact that you are in this class as an engineering student is testament to your abilities. Penalties for scholastic dishonesty are severe and can include, but are not limited to a record in your academic folder, a zero on the assignment/exam, re-taking the exam in question, an F in the course, or expulsion from the University. Don’t jeopardize your career by an act of scholastic dishonesty.

    Details about academic integrity and what constitutes scholastic dishonesty can be found at the website for the UT Dean of Students Office and the General Information Catalog, Section 11-802.

    Course Evaluation

    This course will be evaluated using the standard UT course/instructor evaluation forms during the last week of class. In addition, the instructor will use a few other in-class evaluations.

    Drop Policy

    The fourth day of University classes is the last day of the office add/drop period. After this official period, all course changes must be initiated with the student’s academic dean and must

    have the approval of a departmental advisor and the dean’s representative. Typically drops are not approved unless students can demonstrate "good cause", i.e. health or personal problems that did not exist at the end of the official add and drop period.

    The University of Texas at Austin provides, upon request, appropriate academic adjustments for qualified students with disabilities. For more information, contact the Office of the Dean of Students at 471-6259, 471-4241 TDD or the College of Engineering Director of Students with Disabilities at 471-4321.

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