TXT

vhdl

By Douglas Diaz,2015-04-17 08:23
40 views 0
library ieee; use ieee.std_logic_1164.all; entity bcd is port( A : in std_logic_vector(3 downto 0); Y : out std_logic_vector(6 downto 0) ); end bcd; architecture m1 of bcd is Begin Y <= "1111110" when A="0000" else --0 "0001100" when A="0001" else --1 "1101101" when A="0010" else..
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